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NOCS 2009 : International Symposium on Networks-on-Chips

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Conference Series : Networks-on-Chips
 
Link: http://www.nocsymposium.org/
 
When May 10, 2009 - May 13, 2009
Where La Jolla, CA, USA
Abstract Registration Due Jan 23, 2009
Submission Deadline Jan 30, 2009
Notification Due Mar 13, 2009
Categories    computer architecture   design automation
 

Call For Papers

========================================================================
CALL FOR PAPERS

NOCS 2009: THE 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP
May 10-13, 2009, San Diego, CA

http://circuit.ucsd.edu/~nocs2009/

Sponsored by IEEE CAS/CEDA & ACM SIGARCH/SIGBED/SIGDA
========================================================================

IMPORTANT DATES:
Abstract deadline: January 23, 2009 (hard deadline)
Full paper deadline: January 30, 2009 (hard deadline)
Proposals for tutorials, special sessions, and panels: January 30, 2009
Notification of acceptance: March 13, 2009

NOCS is the premier event dedicated to research on on-chip communication
technology, architecture, design methods and applications. Original
papers describing new and previously unpublished results are solicited
on all aspects of NoC technology. Topics of interest include, but are
not limited to:

- Network architecture (topology, routing, arbitration, ...)
- Network design for 3D stacked logic and memory
- Mapping of applications onto NoCs
- Power and energy issues
- Timing, synchronous/asynchronous communication
- NoC reliability issues
- O/S support for NoCs
- Metrics and benchmarks for NoCs
- Multi/many-core workload characterization & evaluation
- NoC network interface issues
- Modeling, simulation, and synthesis of NoCs
- NoC support for memory and cache access
- NoC design methodologies and tools
- NoC Quality of Service
- NoCs for FPGAs and structured ASICs
- NoC support for CMP/MPSoCs
- Novel interconnect links/switches/routers
- Optical & RF for on-chip/in-package interconnects
- Signaling and circuit design for NoC links
- Physical design of interconnect and NoC
- Floorplan-aware NoC architecture optimization
- Verification, debug & test of NoC
- NoC case studies, application-specific NoC design
- Programming models

Electronic paper submission requires a full paper, up to 10
double-column IEEE format pages, including figures and references.
Papers will be evaluated by the program committee in a blind review
process based on scientific merit, innovation, relevance, and
presentation.

Proposals for tutorial papers and panel sessions are also invited.

A special section related to the theme of the conference will be
organized in collaboration with the IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems.

Organizing Committee:

* General Chairs: Bill Lin (UCSD), Partha Kundu (Intel)
* Program Chairs: Radu Marculescu (CMU), Axel Jantsch (KTH, Sweden)
* Finance Chair: Karam Chatha (Arizona State)
* Registration Chair: Joerg Henkel (U. Karlsruhe, Germany)
* Publications Chair: Luca Carloni (Columbia)
* Publicity Chair: Davide Bertozzi (U. Ferrara, Italy)
* Tutorials Chair: Kees Goossens (NXP & TU Delft, Netherlands)

Program Committee:

* Ahmed Hemani, KTH, Sweden
* Alex Yakovlev, Newcastle U., UK
* Anand Raghunathan, NEC C&C Labs, USA
* Andreas Hansson, TU Eindhoven, Netherlands
* Avinoam Kolodny, Technion, Israel
* Axel Jantsch, KTH, Sweden
* Bill Lin, UCSD, USA
* Brian Towles, D. E. Shaw, USA
* Chita Das, Penn State, USA
* Cristina Silvano, Politecnico di Milano, Italy
* Davide Bertozzi, Univ. of Ferrara, Italy
* Diana Marculescu, CMU, USA
* Dinesh Pamunuwa, Lancaster, UK
* Drew Wingard, Sonics, USA
* Eby Friedman, Univ. of Rochester, USA
* Erik Jan Marinissen, NXP, Netherlands
* Federico Angiolini, Univ. of Bologna, Italy
* Frederic Petrot, TIMA, Grenoble, France
* Gerard Smit, Univ. of Twente, Netherlands
* Hoi-Jun Yoo, KAIST, Korea
* Jan Madsen, DTU, Denmark
* Jari Nurmi, Tampere U. Tech., Finland
* Jens Sparsoe, DTU, Denmark
* Joerg Henkel, Karlsruhe Univ., Germany
* John Bainbridge, Silistix, UK
* Josè Flich, Valencia, Spain
* Karam Chatha, Arizona State, USA
* Kees Goossens, NXP & TU Delft, Netherlands
* Li Shang, Univ. of Colorado, Boulder, USA
* Li-Shiuan Peh, Princeton, USA
* Luca Benini, Univ. of Bologna, Italy
* Luca Carloni, Columbia, USA
* Manolis Katevenis, FORTH and Univ. of Crete, Greece
* Marcello Lajolo, NEC C&C Labs, USA
* Marcelo Lubaszewski, U. Federal Rio Grande do Sul, Brazil
* Michael Taylor, UCSD, USA
* Mike Kishinevsky, Intel, USA
* Nicola Nicolici, McMaster, Canada
* Partha Kundu, Intel, USA
* Partha Pande, Washinton State, USA
* Pascal Vivet, CEA, France
* Peter Feldman, IBM Research, USA
* Petru Eles, Linkoping U., Sweden
* Philippe Martin, Arteris, France
* Radu Marculescu, CMU, USA
* Rajeev Balasubramonian, Univ. of Utah, USA
* Riccardo Locatelli, STM, France
* Robert Mullins, Cambridge, UK
* Shashi Kumar, Jonkoping U., Sweden
* Sri Parameswaran, Univ. New South Wales, Australia
* Srinivasan Murali, EPFL Lausanne, Switzerland
* Sriram Vangal, Intel, USA
* Steve Furber, Manchester, UK
* Sudhakar Yalamanchili, Georgia Tech, USA
* Tapani Ahonen, Tampere, Finland
* Timothy Pinkston, USC, USA
* Twan Basten, TU Eindhoven, Netherlands
* Umit Ogras, Intel, USA
* Vladimir Stojanovic, MIT, USA
* Wayne Wolf, Princeton, USA
* Zhonghai Lu, KTH, Sweden

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