NOCS: Networks-on-Chips

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Past:   Proceedings on DBLP

Future:  Post a CFP for 2019 or later   |   Invite the Organizers Email

 
 

All CFPs on WikiCFP

Event When Where Deadline
NOCS 2018 12th IEEE/ACM International Symposium on Networks-on-Chip
Oct 4, 2018 - Oct 5, 2018 Torino, Italy May 1, 2018 (Apr 24, 2018)
NOCS 2017 11st IEEE/ACM International Symposium on Networks-on-Chip (NOCS)
Oct 19, 2017 - Oct 20, 2017 Seoul, South Korea May 1, 2017 (Apr 24, 2017)
NOCS 2016 10th International Symposium on Networks-on-Chip (NOCS 2016)
Aug 31, 2016 - Sep 2, 2016 Nara, Japan Feb 12, 2016 (Feb 5, 2016)
NOCS 2014 International Symposium on Networks-on-Chip
Sep 17, 2014 - Sep 19, 2014 Ferrara, Italia Mar 2, 2014 (Feb 23, 2014)
NOCS 2013 7th ACM/IEEE International Symposium on Networks-on-Chip
Apr 21, 2013 - Apr 24, 2013 Tempe, Arizona Dec 7, 2012 (Dec 4, 2012)
NOCS 2012 Sixth ACM/IEEE International Symposium on Networks-on-Chip
May 9, 2012 - May 11, 2012 Copenhagen, Denmark Dec 9, 2011 (Dec 2, 2011)
NOCS 2011 International Symposium on Networks-on-Chip
May 1, 2011 - May 4, 2011 Pittsburgh, Pennsylvania, USA Dec 17, 2010 (Dec 10, 2010)
NOCS 2010 International Symposium on Networks-on-Chips
May 3, 2010 - May 6, 2010 Grenoble, France Dec 18, 2009 (Dec 11, 2009)
NOCS 2009 International Symposium on Networks-on-Chips
May 10, 2009 - May 13, 2009 La Jolla, CA, USA Jan 30, 2009 (Jan 23, 2009)
 
 

Present CFP : 2018

The International Symposium on Networks-on- Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, and rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to:

+ NoC Architecture and Implementation:
- Network architecture (topology, routing, arbitration)
- Timing, synchronous/asynchronous communication
- NoC reliability issues and solutions
- Power and thermal issues at the NoC un-core and system-level
- Network interface issues and solutions
- Signaling and circuit design for NoC links and routers

+ NoC for Intelligent Physical Systems:
- Mapping of existing and emerging applications onto NoC
- NoC case studies, application-specific NoC design
- NoC for FPGA, structured ASIC, CMP and MPSoC
- NoC designs for heterogeneous systems, fused CPU-GPU and data-center-on-a-chip (DCoC) architectures
- Scalable modeling of NoC
- Machine learning for NoC and NoC-based Systems

+ NoC and Communication Analysis, Optimization, and Verification:
- NoC performance analysis and Quality of Service
- Modeling, simulation, and synthesis of NoC
- Verification, debug and test of NoC
- NoC design and simulation methodologies and tools
- Metrics, benchmarks, and experiences on NoC-based hardware
- Communication efficient algorithms
- Communication workload characterization and evaluation

+ NoC at the Un-Core and System-level:
- Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoC
- In-memory/In-storage network and NoC for new memory/storage technologies
- NoC support for memory and cache access
- OS support for NoC
- Security issues and solutions in NoC architectures
- Programming models including shared memory, message passing and novel programming models
- Issues related to large-scale systems (datacenters, supercomputers, edge and fog computing) with NoC-based systems as building blocks

+ Novel NoC Technologies
- Optical, wireless, carbon nanotube, and other emerging technologies
- NoC for 3D and 2.5D packages
- Package-specific NoC design
- Network coding and compressed solutions for efficient terabyte NoC architectures
- Approximate computing for NoC and NoC-based systems

+ Inter/Intra-Chip and Rack-Scale Network
- Unified inter/intra-chip networks
- Hybrid chip-scale and rack-scale networks
- All aspects of inter-chip network design
- All aspects of rack-scale network design


Electronic paper submission requires a full paper, up to 8 double-column IEEE format pages, including figures and references. The program committee in a double-blind review process will evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Proposals for special sessions and demos are invited. Paper submissions and demo proposals by industry researchers or engineers to share their experiences and perspectives are also welcome. A percentage of accepted paper will be recommended for publication in an IEEE journal (TBD) after revision according to the review comments. Please find the detailed submission instructions for paper submissions, special session, and demo proposals at the submission page. Further information is available via: https://www.nocs2018.conf.kth.se
 

Related Resources

NOCS 2018   Deadline Extended: 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018)
NOCS 2018   NOCS 2018 - Call for Special Sessions and Tutorials
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