NOCS: Networks-on-Chips

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Past:   Proceedings on DBLP

Future:  Post a CFP for 2018 or later   |   Invite the Organizers Email

 
 

All CFPs on WikiCFP

Event When Where Deadline
NOCS 2017 11st IEEE/ACM International Symposium on Networks-on-Chip (NOCS)
Oct 19, 2017 - Oct 20, 2017 Seoul, South Korea May 1, 2017 (Apr 24, 2017)
NOCS 2016 10th International Symposium on Networks-on-Chip (NOCS 2016)
Aug 31, 2016 - Sep 2, 2016 Nara, Japan Feb 12, 2016 (Feb 5, 2016)
NOCS 2014 International Symposium on Networks-on-Chip
Sep 17, 2014 - Sep 19, 2014 Ferrara, Italia Mar 2, 2014 (Feb 23, 2014)
NOCS 2013 7th ACM/IEEE International Symposium on Networks-on-Chip
Apr 21, 2013 - Apr 24, 2013 Tempe, Arizona Dec 7, 2012 (Dec 4, 2012)
NOCS 2012 Sixth ACM/IEEE International Symposium on Networks-on-Chip
May 9, 2012 - May 11, 2012 Copenhagen, Denmark Dec 9, 2011 (Dec 2, 2011)
NOCS 2011 International Symposium on Networks-on-Chip
May 1, 2011 - May 4, 2011 Pittsburgh, Pennsylvania, USA Dec 17, 2010 (Dec 10, 2010)
NOCS 2010 International Symposium on Networks-on-Chips
May 3, 2010 - May 6, 2010 Grenoble, France Dec 18, 2009 (Dec 11, 2009)
NOCS 2009 International Symposium on Networks-on-Chips
May 10, 2009 - May 13, 2009 La Jolla, CA, USA Jan 30, 2009 (Jan 23, 2009)
 
 

Present CFP : 2017

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to
interdisciplinary research on on-chip, chip-scale, and multichip package scale communication
technology, architecture, design methods, applications and systems. NOCS brings together scientists
and engineers working on NoC innovations and applications from inter-related research communities,
including computer architecture, networking, circuits and systems, packaging, embedded systems, and
design automation. Topics of interest include, but are not limited to:

+ NoC Architecture and Implementation
- Network architecture (topology, routing, arbitration)
- NoC Quality of Service
- Timing, synchronous/asynchronous communication
- NoC reliability issues
- Network interface issues
- NoC design methodologies and tools
- Signaling & circuit design for NoC links

+ NoC Analysis and Verification
- Power, energy & thermal issues (at the NoC, un-core and/or system-level)
- Benchmarking & experience with NoC-based hardware
- Modeling, simulation, and synthesis of NoCs
- Verification, debug & test of NoCs
- Metrics and benchmarks for NoCs

+ Novel NoC Technologies
- New physical interconnect technologies, e.g., carbon nanotubes, wireless NoCs, through-silicon, etc.
- NoCs for 3D and 2.5D packages
- Package-specific NoC design
- Optical, RF, & emerging technologies for on-chip/in-package interconnects
- In-memory network and NoCs for new memory technologies

+ NoC Application
- Mapping of applications onto NoCs
- NoC case studies, application-specific NoC design
- NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
- NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
- Scalable modeling of NoCs

+ NoC at the Un-Core and System-level
- Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoCs
- NoC support for memory and cache access
- OS support for NoCs
- Programming models including shared memory, message passing and novel programming models
- Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

+ On-Chip Communication Optimization
- Communication efficient algorithms
- Communication workload characterization & evaluation
- Energy efficient NoCs and energy minimization

+ Off-Chip and Rack-Level Communication
- All aspects of inter-chip network design
- All aspects of rack-level network design


Electronic paper submission requires a full paper, up to 8 double-column IEEE format pages,
including figures and references. The program committee in a double-blind review process will
evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted
papers must describe original work that has not been published before or is under review by another
conference or journal at the same time. Each submission will be checked for any significant
similarity to previously published works or for simultaneous submission to other archival venues,
and such papers will be rejected. Proposals for special sessions and demos are invited. Paper
submissions and demo proposals by industry researchers or engineers to share their experiences and
perspectives are also welcome. Please find the detailed submission instructions for paper
submissions, special session, and demo proposals at the submission page. Further information is
available via: http://www.arc.ics.keio.ac.jp/nocs17/
 

Related Resources

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IEEE MCSOC 2017   IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip
SBAC-PAD 2017   Symposium on Computer Architecture and High Performance Computing
COMPLEX NETWORKS 2017   6th International Conference on Complex Networks and Their Applications
CAIJ 2017   Computer Applications: An International Journal
ReCoSoC 2017   12th Edition of the International Symposium on Reconfigurable Communication-centric Systems-on-Chip
LHAM 2017   The 5th International Workshop on Legacy HPC Application Migration
ICAISC 2018   International Conference on Artificial Intelligence and Soft Computing
CSA 2017   5th International Workshop on Computer Systems and Architectures
SenSys 2017   ACM Conference on Embedded Networked Sensor Systems