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DFT 2011 : IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Conference Series : Defect and Fault Tolerance in VLSI and Nanotechnology Systems
 
Link: http://www.dfts.org/
 
When Oct 3, 2011 - Oct 5, 2011
Where Vancouver, Canada
Submission Deadline May 14, 2011
Notification Due Jun 29, 2011
Categories    testing   reliability   modeling
 

Call For Papers

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.
The symposium is held yearly, around the world, and this year will be located in Vancouver, British Columbia, Canada.

Conference Topics
The Program Committee cordially invites you to participate and submit your contribution to DFT 2011. The conference topics include, but are not limited to, the following:

Yield Analysis and Modeling
Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics.

Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.

Error Detection, Correction, and Recovery
Self-testing and self-checking solutions; error-control coding; fault masking and avoid- ance; recovery schemes, space/time redundan- cy; hw/sw techniques.
Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, microprocessors.

Dependability Analysis and Validation
Fault injection techniques and environments; dependability characterization.

Defect and Fault Tolerance
Reliable circuit & system synthesis; radiation hardened/tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors.

Repair, Restructuring and Reconfiguration
Repairable logic, reconfiguration, repair; reconfigurable circuit design; DFT for on-line operation; self-healing.

Totally Fail-Safe Design for Critical Applications
Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.

Emerging Technologies
DFT techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.

Paper Submission
Prospective authors should the full paper or an extended summary up to 7 pages using the 6x9 format (details). The accepted file format is PDF. Any other format and manuscripts received in hard-copy form will not be processed. Detailed information about the submission process can be found here.
We are also interested in panel sessions that involve industrial experiences: please send an email to the Program Chairs with a brief description (1 page maximum) of the panel discussion you would like to propose.

Paper Publication and Presenter Registration
Papers will be accepted for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will be included in the IEEE Digital Library. It is mandatory that authors of accepted presentations attend to present their work at the conference and also that each accepted paper is accompanied by at least one full conference registration fee payment (no student registration) before the authors' registration deadline for the manuscript to be included and published in the proceedings.

Best Student Paper Award
All papers with a student as both primary author and presenter will be taken into consideration for the 2011 Best Student Paper Award, sponsored by Intel.

Journal Special Issue
Authors will have the opportunity to submit an extended version of their paper presented at the symposium in a special issue of an archival journal.

Related Resources

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