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AsHES 2020 : The Tenth International Workshop on Accelerators and Hybrid Exascale Systems

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Link: http://www.mcs.anl.gov/events/workshops/ashes/2020
 
When May 17, 2020 - May 17, 2020
Where New Orleans, USA
Submission Deadline Feb 7, 2020
Notification Due Mar 2, 2020
Final Version Due Mar 17, 2020
Categories    hardware architecture   accelerator   HPC   heterogeneous computing
 

Call For Papers

The Tenth International Workshop on Accelerators and Hybrid Exascale
Systems (AsHES)
http://www.mcs.anl.gov/events/workshops/ashes/2020
May 18th, 2020

To be held in conjunction with 34th IEEE International Parallel and
Distributed Processing Symposium in New Orleans, Louisiana USA

Workshop Scope and Goals
========================================
The current computing landscape has gone through an ever-increasing rate
of change and innovation. This change has been driven by the relentless
need to improve the energy-efficient, memory, and compute throughput at
all levels of the architectural hierarchy. Although the amount of data
that has to be organized by today's systems posed new challenges to the
architecture, which can no longer be solved with classical, homogeneous
design. Improvements in all of those areas have led Heterogeneous
systems to become the norm rather than the exception.

Heterogeneous computing leverages a diverse set of computing (CPU, GPU,
FPGA, TPU ...) and Memory (HBM, Persistent Memory, Coherent PCI
protocols, etc ..), hierarchical storage systems and units to
accelerate the execution of a diverse set of applications. Emerging and
existing areas such as DeepLearing, BigData, Cloud Computing,
Edge-Computing, Real-time systems, High-Performance Computing and others
have seen a real benefit due to Heterogenous computer architectures.
These new heterogeneous architectures often also require the development
of new applications and programming models, in order to satisfy these
new architectures and to fully utilize these capacities. This workshop
focuses on understanding the implications of heterogeneous designs at
all levels of the computing system stack, such as hardware, compiler
optimizations, porting of applications, and developing programming
environments for current and emerging systems in all the above-mentioned
areas. It seeks to ground heterogeneous system design research through
studies of application kernels and/or whole applications, as well as
shed light on new tools, libraries and runtime systems that improve the
performance and productivity of applications on heterogeneous systems.

The goal of this workshop is to bring together researchers and
practitioners who are at the forefront of Heterogeneous computing in
order to learn the opportunities and challenges in future Heterogeneous
system design trends and thus help influence the next trends in this area.



Topics of interest for workshop submissions include (but are not limited
to):

* Strategies for programming heterogeneous systems using high-level
models such as OpenMP, OpenACC, SYCL, low-level models such as OpenCL, CUDA;

* Methods and tools to tackle challenges from heterogeneity in
DeepLearing, BigData, Cloud Computing, Edge-Computing, Real-time
Systems, and High-Performance Computing;

* Strategies for application behavior characterization and performance
optimization for accelerators;

* Techniques for optimizing kernels for execution on GPGPU, FPGA, TPU,
and future heterogeneous platforms;

* Models of application performance on heterogeneous and accelerated HPC
systems;

* Compiler Optimizations and tuning heterogeneous systems including
parallelization, loop transformation, locality optimizations, Vectorization;

* Implications of workload characterization in heterogeneous and
accelerated architecture design;

* Benchmarking and performance evaluation for heterogeneous systems at
all level of the system stack;

* Tools and techniques to address both performance and correctness to
assist application development for accelerators and heterogeneous
processors;

* System software techniques to abstract application domain-specific
functionalities for accelerators;
Important Dates (AoE)
========================================
Paper Submission: Feb. 7, 2020
Paper Notification: March. 2, 2020
Camera-Ready: March. 17, 2020

Proceedings
========================================
The proceedings of this workshop will be published electronically
together with IPDPS proceedings via the IEEE Xplore Digital Library.

Papers Submission Guidelines
========================================
Papers should present original research and should provide sufficient
background material to make them accessible to the broader community.

Submitted manuscripts may not exceed 10 single-spaced double-column
pages using 10-point size font on 8.5x11 inch pages (IEEE conference
style), including figures, tables, and references. See the style
templates for latex or word for details.

Submissions will be judged based on relevance, significance,
originality, correctness and clarity.

Submission site: https://easychair.org/conferences/?conf=ashes2020

Journal Special Issue
========================================
The best papers of AsHES 2020 will be invited to a Special Issue on
Topics on Heterogeneous Computing of the Elsevier International Journal
on Parallel Computing (PARCO).

Keynote Speaker
========================================

Best Paper Award
========================================
TBA

Steering Committee
========================================
Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, Stony Brook University, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, Codeplay, UK
James Dinan, Intel Corporation
Sunita Chandrasekaran, University of Delaware, USA
Antonio J. Peña, Barcelona Supercomputing Center, Spain

General Chair
========================================
Min Si, Argonne National Laboratory, USA

Program Co-Chairs
========================================
Lena Oden, FernUniversität in Hagen
Simon Garcia de Gonzalo, Barcelona Supercomputing Center, Spain
Program Committee
========================================
Xiaonan Tian, NVIDIA
Izzat El-Hajj, American University of Beirut
Gaurav Mitra, Texas Instruments Inc.
James Beyer, Nvidia
Ashwin Aji, AMD
Sridutt Bhalachandra, Argonne National Laboratory
Guray Ozen, NVIDIA
Pedro Valero-Lara, The University of Manchester
Nikela Papadopoulou, National Technical University of Athens
Huimin Cui, Institute of Computing Technology, CAS
Seyong Lee, Oak Ridge National Laboratory
Adrián Castelló, Universitat Jaume I
Guido Juckeland, Helmholtz-Zentrum Dresden-Rossendorf (HZDR)
John Leidel, Texas Tech University
Naoya Maruyama, Lawrence Livermore National Laboratory
Stephen Olivier, Sandia National Laboratories
Gabriele Jost, NASA Ames Research Center/CSRA
Khaled Hamidouche, AMD

Questions?
========================================
Please send any queries about the AsHES workshop to ashes@mcs.anl.gov

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