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SELSE 2020 : Call for Papers: The 16th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2020)


When Feb 19, 2020 - Feb 20, 2020
Where Stanford University, CA, USA
Abstract Registration Due Dec 2, 2019
Submission Deadline Dec 9, 2019
Notification Due Jan 10, 2020
Final Version Due Jan 31, 2020
Categories    reliability   high performance computing   security   computer

Call For Papers

The 16th IEEE Workshop on Silicon Errors in Logic – System Effects
SELSE 2020 (
February 19 – February 20, 2020, Stanford University, CA, USA

Important dates:
- Paper Registration (mandatory): December 2, 2019
- Paper Submission (for registered papers): December 9, 2019
- Author Notification: January 10, 2020
- Early Registration: January 17, 2020
- Camera-Ready Submission: January 31, 2020

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high performance applications.

The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.

We are happy to announce that selected SELSE papers will be included in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2020. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Valencia, Spain on June 29 – July 2, 2020.


Key areas of interest include (but are not limited to):
- Error rates and trends in current and emerging technologies, including experimental failure data and the reliability characterization of deployed systems.
- New error mitigation techniques, robust software frameworks, and error handling protocols for resilient system design.
- Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
- Resilience characterization and strategies for machine learning applications, including autonomous vehicles.
- Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
- The design of resilient systems for space exploration.
- The interplay between system security issues and reliability.

Submission Guidelines

Additional information and guidelines for submission are available at Submissions and final papers should be PDF files following the IEEE two-column transactions format with six or fewer printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries---however, they are distributed to attendees of the workshop.

Organizing Committee

General Co-Chairs
John Daly, LPS
Paolo Rech, UFRGS
Laura Monroe, LANL (Emerita)

Program Co-Chairs
Stefano Di Carlo, Torino
Qiang Guan, Kent State
Michael Sullivan, NVIDIA (Emeritus)

Finance Co-Chairs
Sarah Michalak, LANL
Sandhya Chandrashekhar, Cypress

Registration Chair
Karthik Swaminathan, IBM

Local Arrangements Chair
Saurabh Hukerikar, NVIDIA

Publicity Co-Chairs
Michael Sullivan, NVIDIA (North America)
Tiago Balen, UFRGS (South America)
Stefano Di Carlo, PoliTo (Europe)
Yi-Pin Fang, TSMC (Asia)

Bay Area Industry Liaisons
Shahrzad Mirkhani, Bigstream
Mark Gottscho, Google

Vanessa Job, LANL/UNM

Advisors to the Committee
Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD

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