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ADMS 2010 : First International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures


When Sep 13, 2010 - Sep 13, 2010
Where Singapore
Submission Deadline Jun 11, 2010
Notification Due Jul 16, 2010
Final Version Due Aug 9, 2010
Categories    databases

Call For Papers

First International Workshop on Accelerating Data Management Systems Using
Modern Processor and Storage Architectures (ADMS'10)

to be held in conjunction with VLDB 2010

September 13, 2010, Singapore

Important Dates

Paper submission: June 11, 2010
Notification: July 16, 2010
Camera-ready due: August 9, 2010


Workshop Overview

The objective of this one-day workshop is to investigate opportunities in
accelerating data management systems and workloads (which include traditional
OLTP, data warehousing/OLAP, ETL, Streaming/Realtime, and XML/RDF Processing)
using CPU (e.g., commodity and specialized Multi-core, Many-core, GPUs, and
FPGAs), storage systems (e.g., Storage-class Memories like SSDs and
Phase-change Memory), and multicore programming strategies like OpenCL.
The workshop hopes to explore the interplay between overall system design, core
algorithms, query optimization strategies, programming approaches, performance
modelling and evaluation, from the perspective of data management applications.

Topics of Interest

The suggested topics of interest include, but are not restricted to:

* Hardware and System Issues in Domain-specific Accelerators
* New Programming Methodologies for Data Management Problems on Modern Hardware
* Query Processing for Hybrid Architectures
* Autonomic Tuning for Data Management Workloads on Hybrid Architectures
* Algorithms for Accelerating Multi-modal Multi-tiered Systems
* Energy Efficient Software-Hardware Co-design for Data Management Workloads
* Parallelizing non-traditional (e.g., graph mining) workloads
* Algorithms and Performance Models for modern Storage Sub-systems
* Data Layout Issues for Modern Memory and Storage Hierarchies
* New Benchmarking Methodologies for Storage-class Memories

Questions about the conference scope should be directed to the program
co-chairs at

Submission Instructions

All submissions will be handled electronically. More details are posted on
the web site,

The workshop proceedings will be published by VLDB.

It is the authors' responsibility to ensure that their submissions adhere
strictly to the VLDB camera ready format. The paper length is limited to
8 pages. You are permitted a 4 page appendix beyond these 8 pages.
However, reviewers are not required to read this appendix, and the paper
should be self-contained, complete and understandable within the 8 pages.
This 8+4 page rule applies to both submissions and camera-ready.
See for more details and links to the VLDB

Questions about the submission process should be directed to the program
co-chairs at

Organizing Committee

Program Chairs:
* Rajesh Bordawekar, IBM T.J. Watson Research Center
* Christian A. Lang, IBM T.J. Watson Research Center

Program Committee:
* David Bader, Georgia Tech
* Roberto Bayardo, Google
* Brian Cooper, Yahoo! Research
* John Davis, Microsoft Research
* Pradeep Dubey, Intel
* Michael Garland, NVIDIA Research
* Bugra Gedik, IBM Watson Research
* Goetz Graefe, HP Labs
* C Mohan, IBM Almaden Research
* Bongki Moon, University of Arizona
* Jens Teubner, ETH Z?rich
* Philip S. Yu, University of Illinois, Chicago

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