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VLSICS 2019 : International Journal of VLSI design & Communication Systems


When N/A
Where N/A
Submission Deadline Feb 23, 2019
Notification Due Mar 23, 2019
Final Version Due Mar 31, 2019
Categories    VLSI   design   sensor networks   wireless communications

Call For Papers

International Journal of VLSI design & Communication Systems (VLSICS)

Scope and Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas. Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include but are not limited to, the following

  • Design
  • VLSI Circuits
  • Computer-Aided Design (CAD)
  • Low Power and Power Aware Design
  • Testing, Reliability, Fault-Tolerance
  • Emerging Technologies
  • Post-CMOS VLSI
  • VLSI Applications (Communications, Video, Security, Sensor Networks, etc)
  • Nano Electronics, Molecular, Biological and Quantum Computing
  • Intellectual Property Creating and Sharing
  • Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through Email: or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates


Submission Deadline:February 23, 2019
Authors Notification:March 23, 2019
Final Manuscript Due:March 31, 2019
Publication Date:Determined by the Editor-in-Chief

Current Issue

October 2018, Volume 09, Number 05

Static Noise Margin Optimized 11nm Shorted-Gate and Independent-Gate Low Power 6T FINFET SRAM Topologies

DustenVernor, Santosh Koppa and Eugene John, University of Texas at San Antonio, USA

UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core

Lakhan Shiva Kamireddy1 and Lakhan Saiteja K2, 1University of Colorado, USA and 2Indian Institute of Technology - Kharagpur, India

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