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ULIS 2010 : 11th International Conference on Ultimate Integration on Silicon


When Mar 17, 2010 - Mar 19, 2010
Where Glasgow, Scotland
Submission Deadline Feb 1, 2010
Notification Due Feb 11, 2010
Final Version Due Feb 1, 2010
Categories    electron devices   semiconductor   electronics   physics

Call For Papers

The aim of the ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.
This year's edition will feature a workshop on 'High Mobility nMOS Substrates: Strained Si, Ge or III-V?'.

Accepted papers will be published in the Conference Proceedings (on paper) and on IEEExplore.
A limited number of the best oral papers presented at the conference will be selected for publication in a special issue with peer review of Solid State Electronics.

Scientific Programme:

Topics for original contributions to be submitted to the ULIS 2010 Conference include, but are not limited to:

* Nanometer scale devices: physics, technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
* CMOS scaling perspectives; device / circuit level performance evaluation; switches and memory scaling.
* New channel materials for CMOS electronics: strained Si, strained SOI, SiGe, GOI, III-V and high mobility materials for MOSFET; carbon based electronics; carbon nanotubes; graphene based devices.
* Thin gate dielectrics: first and second generation high-k materials for switches and memory.
* Alternative transistor architectures including PDSOI, FDSOI, DGSOI, FinFETs, MuGFETs, vertical MOSFET, IMOS and tunnel FET structures. Benchmarking of new architectures w.r.t. bulk CMOS.
* One dimensional and zero dimensional structures: nanowires, nanotubes, nanodots. Nanowire and nanotube based interconnects; nanocrystal based NVM memory cells.
* Variability and fluctuation phenomena in electronic switches and memory devices. Single electron, few electron, discrete dopant and discrete charge effects in scaled electron devices.
* Advanced physics based modeling and simulation of nanoscale switches and memory. First principle and ab-initio modeling of devices, materials and interfaces for CMOS.
* Quasi ballistic, ballistic and quantum transport in nanoscale devices. Compact modeling of nanoscale devices. Modeling and management of thermal effects. Benchmarking of modeling approaches.
* Process characterization through device parameter extraction, device and electrical characterization of nanometer scale technologies.
* CMOS compatible molecular and quantum devices; non conventional nanodevices for sensors, actuators and bioelectronics. NanoCMOS to bio- and opto- interfaces.

Invited Speakers:

Four distinguished invited speakers from America, Asia and Europe will open the sessions of the two-day conference programme providing long term views of nanoelectronics development worldwide.


A workshop session will be organized on 17th March 2010 as part of the conference, in collaboration with the Training Program of the NanoSIL project. The title of this workshop is 'High Mobility nMOS Substrates: Strained Si, Ge or III-V?'


The deadline for submission of your four-page camera-ready papers in IEEE double-column format is 1st February 2010.


If you have any enquiries about the conference then please email Scott Roy, the conference chair, at

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