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H2RC 2018 : 4th Workshop on Heterogeneous High-performance Reconfigurable Computing

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Link: http://h2rc.cse.sc.edu
 
When Nov 11, 2018 - Nov 11, 2018
Where Dallas, TX
Submission Deadline Aug 15, 2018
Notification Due Sep 18, 2018
Final Version Due Oct 15, 2018
Categories    FPGA   HPC   supercomputing   parallel computing
 

Call For Papers

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** Call for Papers **
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Fourth International Workshop on
Heterogeneous High-performance Reconfigurable Computing (H^2RC)
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Held in conjunction with Supercomputing 2018
Sunday Morning, November 11, 2018
Dallas, TX
http://h2rc.cse.sc.edu
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Submission Deadline:
August 15, 2018 (1 to 4 page extended abstracts)
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As conventional von-Neumann architectures are suffering from rising
power densities, we are facing an era with power, energy efficiency, and
cooling as first-class constraints for scalable HPC. FPGAs can tailor
the hardware to the application, avoiding overheads and achieving higher
hardware efficiency than general-purpose architectures. Leading FPGA
manufacturers have recently made a concerted effort to provide a range
of higher-level, easier to use high-level programming models for FPGAs.

Such initiatives are already stimulating new interest within the HPC
community around the potential advantages of FPGAs over other
architectures. With this in mind, this workshop, now its fourth year,
brings together HPC and heterogeneous-computing researchers to
demonstrate and share experiences on how newly-available high-level
programming models, including OpenCL, are already empowering HPC
software developers to directly leverage FPGAs, and to identify future
opportunities and needs for research in this area.
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Topics
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Submissions are solicited that explore the state of the art in the use
of FPGAs in heterogeneous high-performance compute architectures and, at
a system level, in data centers and supercomputers. FPGAs may be
considered from either or both the distributed, parallel and composable
fabric of compute elements or from their dynamic reconfigurability. We
particularly encourage submissions which focus on the mapping of
algorithms and applications to heterogeneous FPGA-based systems as well
as the overall impact of such architectures on the compute capacity,
cost, power efficiency, and overall computational capabilities of data
centers and supercomputers. A non-comprehensive list of potential
topics of interest is given below:

1. FPGAs in the cloud and data center
2. Cloud and data center applications
3. Leveraging reconfigurability
4. Benchmarks
5. Implementation studies
6. Programming languages, tools, and frameworks
7. Future-gazing
8. Community building
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Special theme for 2018
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For this year's workshop we especially encourage the submission of
papers on the topic of FPGA-based support for non-volatile memory and
near-memory computing.

Non-volatile memory (NVM) technologies such as Flash and Phase-Change
memory potentially facilitate shared storage in the microsecond regime.
In emerging systems, NVM may serve as a new level of memory hierarchy or
as a networked resource. To this end, early work in developing both
system-level interfaces to NVM (such as NVMe) and network-level
interfaces to NVM (such as RDMA over Converged Ethernet 2) rely heavily
on FPGAs as low-latency intermediaries.
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Prospective authors are invited to submit relevant contributions as an
extended abstract in ACM SIG Proceedings format of up to four pages.

You can submit your contribution(s) through a link on the H2RC website:
http://h2rc.cse.sc.edu

The authors of accepted papers will be invited to present their work at the workshop.
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Important dates:
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Submission Deadline: August 15, 2018
Acceptance Notification: September 18, 2018
Camera-ready Manuscripts Due: October 15, 2018
Workshop Date: November 11, 2018
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Workshop Format:
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H2RC is a half-day Sunday workshop. It will be comprised of:
-- Keynote and invited talks
-- Talks selected among paper submissions
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Organizing Committee:
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Michaela Blott, Xilinx
Franck Cappello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Jason D. Bakos, University of South Carolina
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Technical Program Committee:
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Rizwan Ashraf, Oak Ridge National Laboratory
Paul Chow, University of Toronto
Hans Eberle, NVIDIA
Ken Eguro, Microsoft Research
Xin Fang, Northeastern University
Alan George, University of Pittsburgh
Christoph Hagleitner, IBM
Andreas Koch, TU Darmstadt
Miriam Leeser, Northeastern University
Chistian Plessl, University of Paderborn
Viktor Prasanna, University of Southern California
Marco Santambrogio, Politecnico Di Milano
Yaman Umuroglu, Xilinx Research

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