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WAMCA 2018 : 9th Workshop on Applications for Multi-Core Architectures (WAMCA2018) at Lyon (France) - Deadline 15 June 2018


When Sep 21, 2018 - Sep 24, 2018
Where Lyon - FRANCE
Submission Deadline Jun 15, 2018
Notification Due Jul 10, 2018
Final Version Due Jul 20, 2018
Categories    HPC   multicore   manycore   parallelism

Call For Papers

9th Workshop on Applications for Multi-Core Architectures (WAMCA2018) at Lyon (France) - Deadline 15 June 2018

[Please accept our apologies if you receive multiple copies of this CFP]

WAMCA2018: Workshop on Applications of Multi-Core Architectures
Ecole Nationale Supérieure de Lyon
Lyon, France, September 21-24, 2018

in conjunction with SBAC-PAD 2018

Submission link:

* Submission of manuscripts: June 15, 2018
* Notification of acceptance: July 10, 2018
* Preliminary camera-ready version: July 20, 2018
* Date of workshop: September 21-24, 2018
* Journal Special Issue first version: November 1, 2018

Since the advent of the multi-core concept, significant advances have been made on many of the related aspects. Multi-core has become a natural element in the HPC ecosystem, and its pervasiveness within the landscape of common computing devices has made it a standard. Therefore, hardware and software concerns related to multi-core are good targets for computer science investigations, with a high potential for a genuine contribution. Beside the plethora of applications for which more powerful solutions are still expected, efficient implementation techniques for many-core chip processors are of keen interest. WAMCA is aiming at providing an opportunity to address all aforementioned technical challenges and more, including reports on specific case studies. This workshop is an opportunity for application designers and computer architects to discuss new techniques and emerging applications as well as their implications on current and next-generation many-core architectures. Authors are invited to submit manuscripts reporting a technical contribution on multi-core related topics. Aspects of interest include (but are not limited to):
+ Multithread parallelisation
+ Scalability issues
+ Case study
+ Hybrid parallelisation
+ NUMA manycore implementation
+ Benchmarking and runtime analysis
+ Frameworks and tools
+ Foundation of shared memory computing

Submissions must be in English, 8 pages maximum, following the IEEE conference formatting guidelines (submission). All accepted papers will be published at IEEE Xplore and selected ones will be considered for a publication in the International Journal of High Performance Computing and Networking (IJHPCN).

Workshop Chairs
Claude Tadonki (MINES ParisTech - PSL)
Cristiana Bentes (State University of Rio de Janeiro)
Guido Araujo (State University of Campinas)
Lucia Drummond (Fluminense Federal University)
Mauricio Pilla (Federal University of Pelotas)
Phillippe Navaux (Federal University of Rio Grande do Sul)
Ricardo Farias (Federal University of Rio de Janeiro)

Program Committee
Alexandre Gonçalves (IFRJ - Brazil)
Alexandre Nery (UnB - Brazil)
Andre Rauber Du Bois (UFPEL - Brazil)
Corinne Ancourt (Mines ParisTech - France)
Costin Iancu (Lawrence Berkeley National Lab - USA)
Denis Barthou (INRIA - France)
Diego Brandao (CEFET-RJ - Brazil)
Diego Dutra (UFRJ - Brazil)
Eyder Rios (UESPI - Brazil)
Gabriele Mencagli (University of Pisa - Italy)
Guido Araujo (UNICAMP - Brazil)
Guilherme Cox (Rutgers University - US)
Henrique Freitas (PUC MG - Brazil)
Igor Machado (UERJ - Brazil)
Juliana Silva Zamith (UFRRJ - Brazil)
Khaled Ibrahim (Lawrence Berkeley National Lab - USA)
Konstantin Petrov (INRIA - France)
Leandro Marzulo (UERJ - Brazil)
Leonel Sousa (INESC-ID - Portugal)
Mauricio Pilla (UFPEL - Brazil)
Marcelo Zamith (UFRRJ - Brazil)
Marcin Paprzycki (IBS PAN and WSM - Poland)
Mitsuhisa Sato (RIKEN AICS / University of Tsukuba - Japan)
Rodolfo Azevedo (UNICAMP - Brazil)
Sandro Rigo (UNICAMP - Brazil)

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