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DRSN 2018 : International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks

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Link: http://tytra.org.uk/drsn/
 
When Jul 17, 2018 - Jul 19, 2018
Where Orleans, France
Submission Deadline Apr 22, 2018
Notification Due May 1, 2018
Final Version Due May 11, 2018
Categories    FPGA   HPC   reconfigurable   networks
 

Call For Papers

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DRSN-2018
International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks
http://tytra.org.uk/drsn/

July 17 – July 19, 2018
Orleans, France

[as part of The International Conference on High Performance Computing & Simulation (HPCS 2018)]

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Quick Links
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Workshop: http://tytra.org.uk/drsn/
Submission: https://easychair.org/conferences/?conf=drsn2018
Parent Conference: http://hpcs2018.cisedu.info/

Important Dates
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Paper submissions: April 22, 2018 **EXTENDED**
Acceptance notification: May 01, 2018
Camera-ready papers and registration due: May 11, 2018
Workshop date: July 17 – 19, 2018
(workshop will be on one of these dates)

About
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The International Workshop on High Performance & Dynamic Reconfigurable Systems and Networks (DRSN-2018) is intended to serve as a forum and bring together researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of reconfigurable systems and networks in high-performance systems. The challenges to wider adoption of these technologies, arising out of heterogeneity, programming environments, compilers, and run-time systems are of special interest to this workshop, along with innovations at the architectural level.

This workshop is part of the International Conference on High Performance Computing & Simulation (HPCS 2018, http://hpcs2018.cisedu.info/), and all accepted papers are published with the parent conference’s proceedings on IEEE.

Topics of Interest
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The DRSN Workshop topics of interest include (but are not limited to) the following:

* Heterogeneous High Performance Computing (HHPC) and High performance Reconfigurable Computing (HPRC) Applications
- HPC applications on multi/many-core CPUs, GPUs and FPGAs
- HHPC and HPRC for Scientific Applications
- HHPC and HPRC for Machine Learning and Artificial Intelligence
- HHPC and HPRC for Big-Data Applications
- FPGAs for Edge Computing and Bump-in-the-Wire

* Tools, Languages, Frameworks, Benchmarks, and DSE
- Compilation, Programming Languages, and DSLs for HHPC and HPRC
- Tools, Frameworks, Design-flows for HHPC and HPRC
- VMs, Middleware, Run-time and Operating Systems for HHPC & HPRC
- Domain Specific Languages (DSLs) for HHPC and HPRC
- High-level and Pure Software Programming for Reconfigurable Devices
- Design Space Exploration (DSE) of Reconfigurable and/or NoC-based systems
- Self-reconfiguration and self-optimization for HPC

* Benchmarks and Evaluations
- Benchmarks: Compute performance and/or power/cost efficiency in cloud/HPC
- Area, energy, and performance evaluation
- Comparative analysis of heterogeneous devices and frameworks for HPC

* Networks and NoCs
- Novel NoC Architectures for high-performance systems
- Systems software support for advanced NoC-based systems
- NoC-aware compilation and runtime systems
- Mapping and scheduling for NoC-based systems
- Implementation case studies of reconfigurable and NoC-based systems

* Other
- Reliability, scalability, availability, and fault tolerance
- Reconfigurable computing education

Publication
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Accepted papers will be published in the Conference proceedings of the host conference, HPCS 2018. Instructions for final manuscript format and requirements will be posted on the HPCS 2018 Conference web site. As in the past, we plan to include the proceedings in the IEEE Digital Library and have it indexed in all major indexing services accordingly.

Plans are underway to have the best papers, in extended version, selected for possible publication in a reputable journal as special issue. Detailed information will soon be announced and will be made available on the conference website.

Instructions for Authors
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You are invited to submit original and unpublished research on the topics of interest, and other topics related to dynamic reconfigurable systems and networks. Submitted papers must not have been published or simultaneously submitted elsewhere.

*Regular papers*: please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors’ names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript.

*Poster papers*: Short poster papers (3-6 pages) will also be considered (please refer to http://hpcs2018.cisedu.info/1-call-for-papers-and-participation/call-for-posters for posters submission details).

HPCS 2018, which is our host conference, uses IEEE manuscript templates for conference proceedings. For paper formatting instructions and *templates*, please refer to the instructions on the HPCS website here: http://hpcs2018.cisedu.info/6-participants/author-s-info-hpcs2018

Submit a PDF copy of your full manuscript to the workshop paper submission EasyChair site at https://easychair.org/conferences/?conf=drsn2018.
Please make sure you prepare your paper for *blind reviews*.

Paper Review and Presentation
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Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity and presentation, and references. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend the HPCS 2018 conference (http://hpcs2018.cisedu.info/) to present the paper at the workshop.

Keynote Speaker
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Dr Herman Lam
Associate Director of CHREC, the NSF Center for High-Performance Reconfigurable Computing
University of Florida

Technical Program Committee
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Hideharu Amano, Keio University, Japan
El-Bay Bourennanne, Université de Bourgogne, France
David Castells-Rufas, Universidad Autonoma de Barcelona, Spain
Sairahul Chalamalasetti, Hewlett Packard, USA
Rene Cumplido, INAOE, Mexico
Masoud Daneshtalab, KTH Royal Institute of Technology, Sweden
Diana Göhringer, TU Dresden, Germany
Martin Herbordt, Boston University, Massachusetts, USA
Michael Huebner, Ruhr-Uni­ver­si­tät Bo­chum, Germany
Miriam Leeser, Northeastern University, Massachusetts, USA
Martin Margala, University of Massachusetts – Lowell, Massachusetts, USA
Stephen Neuendorffer, Xilinx Inc, USA
Jari Nurmi, Tampere University of Technology, Finland
Andres Ortero, Universidad Politécnica de Madrid, Spain
Muhammad Adeel Pasha, Lahore University of Management Sciences (LUMS), Pakistan
Kyprianos Papadimitriou, TEI of Crete, Greece
Hiren Patel, University of Waterloo, Canada
Sebastien Pillement, Université de Nantes, France
Thilo Pionteck, Otto-von-Guericke Universität Magdeburg, Germany
Hassan Rabah, Université de Lorraine, France
Ann Gordon-Ross, University of Florida, USA
Oren Segal, Hofstra University, New York, USA
Rahul R. Sharma, Intel Corporation
Zain Ul-Abdin, Halmstad University, Sweden
Dirk Stroobandt, Ghent University, Belgium
Aaron Smith, Microsoft Research, USA
Andres Upegui, École Spécialisée de Suisse Occidentale, Switzerland
Wim Vanderbauwhede, University of Glasgow, UK


Organizers
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Syed Waqar Nabi, University of Glasgow, UK
Nasibeh Nasiri, Intel Corporation, CA
Gilberto Ochoa-Ruiz, Universidad Autónoma de Guadalajara (UAG), Mexico

Contact
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Please find contact details of workshop organizers here: http://tytra.org.uk/drsn/committees/

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