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CPMT 2010 : IEEE CPMT Symposium Japan, formerly VLSI Package Workshop in Japan


When Aug 24, 2010 - Aug 26, 2010
Where Tokyo, Japan
Submission Deadline Feb 15, 2010
Notification Due Mar 31, 2010
Final Version Due May 15, 2010
Categories    manufacturing

Call For Papers

The Leading International Symposium on Components, Packaging, and Manufacturing Technology
IEEE CPMT Symposium Japan
( Formerly “VLSI Packaging Workshop in Japan” )
Aug. 24-26, 2010

Sanjo Conference Hall, The University of Tokyo, Tokyo, JAPAN

Sponsored by the IEEE CPMT Society Advanced industrial science and technology (AIST)

“The VLSI Packaging Workshop in Japan” held every other year since 1992 has become a well-known international workshop for advanced packaging technologies. Due to ever increasing activities and changing demands, the committee has reviewed its mission, cooperated with the members of IEEE CPMT Japan Chapter, refurbished the workshop, and started the new symposium - IEEE CPMT Symposium Japan. It will provide component, packaging, and manufacturing researchers who are extending their activities beyond borders with opportunities to exchange technical knowledge and perspective. The committee strongly encourages you to attend this symposium and participate in the discussion, to understand the technology trends and find the best targets for your technology / business development. Bring your latest research results and share with the participants who are experts from the industry and the grove of Academe, and discuss with them. Anybody contributing to the achievement of a sustainable society through electronics is very welcome at this symposium.

◆ 3D Packaging & Chip on Chip
◆ Advanced Fine Pitch Packaging
◆ Assembly and Packaging Challenges for Cu/Low-k Chips
◆ Borad level reliability System in a Package (SiP)
◆ Electrical Performance & Thermal Management
◆ Emerging Technologies
◆ Failure Mechanisms & Reliability Improvement
◆ Green Material
◆ Integrated Passives / Embedded Components
◆ Laminated Materials & Processing
◆ Materials for High Speed Application & Wafer Process
◆ MEMS Packaging
◆ Micro Bumping Technology
◆ Nano-Technology
◆ Packaging for Automobile
◆ Packaging for Optoelectronics
◆ RF Components & Modules / RF Tags
◆ System in a Package (SiP)
◆ Wafer Level CSP
You are invited to submit a 500-word abstract to the program chair with the reference of maximum two diagrams.
Acceptance will be notified by Mar. 31st.
Abstract due: Feb 15th, 2010

Submit to: Program Chair:
  Dr. Shigenori Aoki

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