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MICRO 2018 : The 51st Annual IEEE/ACM International Symposium on Microarchitecture

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Conference Series : International Symposium on Microarchitecture
 
Link: https://www.microarch.org/micro51/
 
When Oct 20, 2018 - Oct 24, 2018
Where Fukuoka, Japan
Abstract Registration Due Mar 30, 2018
Submission Deadline Apr 6, 2018
Notification Due Jul 18, 2018
Categories    microarchitecture
 

Call For Papers

The 51st International Symposium on Microarchitecture is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers and we aim to continue this tradition at MICRO-51. In 2018, MICRO goes to Fukuoka, Japan.

We invite original paper submissions related to (but not limited to) the following topics:

Processor, memory, interconnect, and storage architectures.
Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies.
Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, cost, complexity, predictability, quality of service, reliability, dependability, security, scalability, programmer productivity, etc.
Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc.
Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc.
Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, near-data and in-memory accelerators, etc.
Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP).
Compiler optimizations and microarchitecture techniques for heterogeneous architectures including CPU+GPUs, GPUs, SoCs, and programmable accelerators.
Microarchitecture techniques to better support system software, programming languages, programmability, and compilation.
Architectures and compilers for embedded processors, DSPs, GPUs, ASIPs (network processors, multimedia, wireless, etc.).
Low-power, high-performance, and cost/complexity-efficient architectures.
Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc.
Advanced software/hardware speculation and prediction schemes.
Microarchitecture modeling and simulation methodology.
Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads.

Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review.

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