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SLIP 2018 : 20th IEEE/ACM International Workshop on System-Level Interconnect Prediction


Conference Series : System-Level Interconnect Prediction
When Jun 23, 2018 - Jun 23, 2018
Where San Francisco
Abstract Registration Due Mar 11, 2018
Submission Deadline Mar 18, 2018
Notification Due Apr 22, 2018
Final Version Due May 1, 2018
Categories    interconnect   communication   cyber-physical systems   design automation

Call For Papers

20th IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2018)
Co-located with ACM/IEEE Design Automation Conference
June 23 2018, Saturday
Moscone Center West, San Francisco, CA
Co-sponsored by the ACM SIGDA and the IEEE Computer Society

General Chair: Shiyan Hu, Linnaeus University, Sweden
Technical Program Chair: Huafeng Yu, Boeing, USA
Technical Program Co-Chair: Chengmo Yang, Univ. of Delaware, USA
Finance Chair: Amlan Ganguly, Rochester Inst. of Technology, USA
Publicity Chair: Yanzhi Wang, University of Syracuse, USA
Panel Chair: Selcuk Kose, University of South Florida, USA
Publications Chair: Bei Yu, CUHK, Hong Kong

Steering Committee Members:
• Chuck Alpert, Cadence, USA
• Deming Chen, UIUC, USA
• Chung-Kuan Cheng, UCSD, USA
• Andrew B. Kahng, UCSD, USA
• Michael Kishinevsky, Intel, USA
• Baris Taskin, Drexel Univ., USA
• Rasit O. Topaloglu, IBM, USA
• Tsung-Yi Ho, NTHU, Taiwan

The general technical scope of the workshop is the design, analysis, prediction, and optimization of interconnect and communication fabrics in electronic systems. The organizing committee invites original contributions to the workshop. These contributions include papers, tutorials, panels, special sessions, and posters. We accept papers based on novelty and contributions to the advancement of the field. The accepted papers will be published in the ACM and IEEE digital libraries.

Technical topics include but are not limited to:

• Interconnect prediction and optimization at various IC and system design stages
• System-level design for FPGAs, NoCs, reconfigurable systems
• Design, analysis, and optimization of power and clock networks
• Interconnect reliability Interconnect topologies and fabrics of multi- and many-core architectures
• Design-for-manufacturing (DFM) and yield techniques for interconnects
• High speed chip-to-chip interconnect design
• Design and analysis of chip-package interfaces
• Power consumption of interconnects
• 3D interconnect design and prediction
• Applications of interconnects to social, genetic, and biological systems
• Co-optimization of interconnect technology and chip design
• Emerging interconnect technologies in machine learning platforms & chips


We invite authors to submit papers of 4 to 8 pages, double-columned, 9pt or 10pt font in ACM proceedings format available at

To permit double blind review, all papers must remove author information (submissions with author information will be rejected). Authors should submit papers electronically:

Student Awards:

Provided by the IEEE Computer Society’s Technical Committee on VLSI (TCVLSI), the Best Student Paper Award will be awarded for a SLIP2018 paper whose first author is a student. In addition, limited student travel grants of $250 are available. Details will follow on the website.


The workshop includes keynotes, regular paper sessions, interactive panels, tutorials, invited talks, and interactive poster sessions. Our program also includes lunch, refreshments, and a traditional social dinner with fun elements.

Important Dates:

Abstract Registration: Mar 11, 2018
Paper Submission: Mar 18, 2018
Author Notification: April 22, 2018
Final Version Upload: May 1, 2018

For any questions, please contact:
Huafeng Yu (

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