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DFT 2018 : IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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Conference Series : Defect and Fault Tolerance in VLSI and Nanotechnology Systems
 
Link: http://www.dfts.org/
 
When Oct 8, 2018 - Oct 10, 2018
Where Chicago, IL, USA
Abstract Registration Due May 4, 2018
Submission Deadline May 18, 2018
Notification Due Jul 6, 2018
Final Version Due Jul 27, 2018
Categories    reliability   dependability   VLSI   circuits
 

Call For Papers

=== ABOUT DFT ===
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

=== IMPORTANT DATES ===
- Abstract submission: May 4, 2018
- Full paper submission: May 18, 2018
- Acceptance notification: July 6, 2018
- Camera ready deadline: July 27, 2018

=== PROGRAM TOPICS ===
The topics include (but are not limited to) the following ones:

1. YIELD ANALYSIS AND MODELING
Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
2. TESTING TECHNIQUES
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
3. DESIGN FOR TESTABILITY IN IC DESIGN
FPGA, SoC, NoC, ASIC, low power design and microprocessors.
4. ERROR DETECTION, CORRECTION, AND RECOVERY
Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural-specific techniques, system-level design-time or runtime strategies.
5. DEPENDABILITY ANALYSIS AND VALIDATION
Fault injection techniques and frameworks; dependability and characterization.
6. REPAIR, RESTRUCTURING AND RECONFIGURATION
Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
7. DEFECT AND FAULT TOLERANCE
Reliable circuit/system synthesis; radiation hardened and/or tolerant processes and design; design space exploration for dependable systems, transient/soft faults and errors.
8. AGING AND LIFETIME RELIABILITY
Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
9. DEPENDABLE APPLICATIONS AND CASE STUDIES
Methodologies and case study applications to Internet of Things, automotive, railway, avionics and space, autonomous systems,
industrial control, etc.
10.EMERGING TECHNOLOGIES
Techniques for 2.5D/3D ICs, quantum computing architectures, memristors, spintronics, microfluidics, etc.
11.DESIGN FOR SECURITY
Fault attacks, fault tolerance-based countermeasures, scan-based attacks and counter-measures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.

=== PAPER SUBMISSIONS ===
Prospective authors are invited to submit original and unpublished contributions. Two types of submissions are possible: (i) regular papers (6 pages), and (ii) short papers (4 pages). Both types will be included in the symposium proceedings and should adhere to the IEEE conference template, 2-columns style (available on conference web site), and submitted as a PDF file, electronically. Please refer to the symposium web page for updated information.

=== CALL FOR SPECIAL SESSIONS ===
Proposals for Special Sessions are also invited. For more information, visit symposium website and see the specific call.

=== PAPER PUBLICATION ===
Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library. All papers will be considered for the DFT 2018 Best Paper Award. Furthermore, selected papers will be considered for a special issue/section of an archival journal.

=== VENUE ===
The symposium is going back to North America on its 31st edition and will take place in the USA at the Wyndam Grant Hotel, Chicago Waterfront, on the south end of the Magnificent mile, on Chicago river. The Chicago metropolitan area has nearly 10 million people and is the third-largest in the United States. Chicago has often been called a global architecture capital and is considered one of the most important business centers in the world.

=== ORGANIZATION ===
- General co-chairs:
* Spyros Tragoudas (Southern Illinois University, US - spyros@siu.edu)
* Saqib Khursheed (University of Liverpool, UK - S.Khursheed@liverpool.ac.uk)

- Program co-chairs:
* Marco Ottavi (Università di Roma "Tor Vergata", IT - marco.ottavi@uniroma2.it)
* Vilas Sridharan (AMD, US - vilas.sridharan@amd.com)

- Publicity chair:
* Mihalis Psarakis (University of Piraeus, GR - mpsarak@unipi.gr)

- Publication chair:
* Rishad Shafik (Newcastle University, UK - Rishad.Shafik@newcastle.ac.uk)

- Industrial liaison chair:
* Prashant Joshi (Cadence, USA - prashant.joshi@gmail.com)

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