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SELSE 2018 : The 14th IEEE Workshop on Silicon Errors in Logic - System Effects


When Apr 3, 2018 - Apr 4, 2018
Where Boston, Massachusetts, USA
Abstract Registration Due Dec 20, 2017
Submission Deadline Jan 12, 2018
Notification Due Feb 16, 2018
Final Version Due Mar 1, 2018

Call For Papers

The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching especially in safety-critical applications like aerospace and automotive. Growing concern about transient errors, unstable storage cells, and the effects of aging are influencing system and application design. While the computational capabilities of emerging logic and memory device technologies are attractive for several safety-critical applications and new computing philosophies like deep learning become popular, they introduce several reliability challenges that need to be addressed. Additionally, reliability is a key issue for large-scale systems, such as those in data centers and cloud computing infrastructure. This year, we also welcome papers on the system security issues as they relate to and impact system reliability.
The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions. SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also solicited.

Key areas of interest are (but not limited to):
- Technology trends and their impact on error rates.
- New error mitigation techniques.
- Error handling protocols (higher-level protocols for robust system design).
- Characterizing the overhead and design complexity of error mitigation techniques.
- Case studies describing the tradeoff analysis for reliable systems.
- System-level models: derating factors and validation of error models.
- Experimental data on failures in current and emerging technologies and applications
- Characterization of reliability of systems deployed in the field and mitigation of issues.
- Software-level impact of hardware failures.
- Software frameworks for resilience.
- Impact of machine learning components on system resilience.
- Resilient accelerator-rich systems.
- Inexact or approximate computing as it relates to system errors.
- (New) Cross-layer resilience techniques.
- (New) System security issues that impact and interact with system reliability.

Submission Guidelines
Additional information and guidelines for submission are available at Submissions and final papers should be in PDF following IEEE two-column transactions format that does not exceed six printed pages of text; the bibliography does not count against this page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries - however, they are distributed to attendees of the workshop. Authors have the option of making their presentation slides available on the SELSE website, but this is not mandatory.

Organizing Committee

General Co-Chairs
- Siva Hari, NVIDIA
- Laura Monroe, LANL

Program Co-Chairs
- Paolo Rech, UFRGS
- Karthik Pattabiraman, UBC

Finance Co-Chairs
- Laura Monroe, LANL
- Steven Raasch, AMD

Publicity Co-Chairs
- Michael Sullivan, NVIDIA
- Tiago Balen, UFRGS
- Stefano Di Carlo, PoliTo
- Yi-Pin Fang, TSMC

Documents Chair
- Fritz Previlon, Northeastern University

Industry Liaison
- Jon Stephan, Intel

- Masab Ahmad, UCONN
- Omer Khan, UCONN

Local Arrangements Chair
- Devesh Tiwari, Northeastern University

Advisors to the Committee
- Sarah Michalak, LANL
- Alan Wood, Oracle
- Vilas Sridharan, AMD
- Adrian Evans, iRoC

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