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3rd Workshop on Advanced Interconnect Solutions and Technologies
for Emerging Computing Systems

Monday January 22nd, 2018, Manchester, UK
Held in conjunction with HiPEAC 2018

CALL FOR PAPERS

http://mpsoc.unife.it/~aistecs/

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The AISTECS workshop promotes research and knowledge exchange on evolutionary as well as revolutionary interconnect technologies, in the perspective of interconnects adoption at all scales: from high-performance computing systems and datacenters down to embedded devices and the Internet of Things.

Interconnects are subject to growing expectations in terms of performance and Quality of Service while being tied to shrinking power and cost budget, as well as thermal envelopes. To this end, the exploration of emerging interconnect technologies along with the design of disruptive/novel ideas at the microarchitectural network level are necessary. Both approaches lead to crucial challenges and interesting design tradeoffs that must be identified to enable widespread adoption of emerging technologies in next-generation computing platforms. Novel interconnect features may also disrupt the expected shape of future computer systems from the design point of view and also from the programmability and/or runtime management perspectives.

The AISTECS workshop aims to foster development of advanced interconnect solutions, for emerging computing systems, and using emerging technologies. To this aims, the workshop gathers a complete range of perspectives, spanning from raw technology issues and solutions up to studies at the overall system level of modern multi-/many-core systems. This encompasses novel network solutions from both academic and industrial researchers.

IMPORTANT DATES
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Submission deadline (hard): Thursday November 23th 2017, anywhere on earth (AOE).
Notification: December 8th 2017
Camera-ready December 22nd 2017

TOPICS OF INTEREST
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● Communication infrastructures for HPC systems, Supercomputers and Data Centers
● Near range interconnects
● Networks on Chip (NoCs)
● Memory interconnect and coherence support
● Network architectures (topology, control-flow, routing, etc.)
● Integrated photonics based interconnects
● Silicon Interposer solutions and embedded multi-die interconnects
● Interconnect solutions for heterogeneous GPU/FPGA-based multi/macro-chip systems
● Emerging interconnect technologies (EIT): photonics, carbon nanotubes, through-silicon, RF, wireless NoC
● Crucial challenges and design tradeoffs for EIT in future computer systems
● Low-level technological improvements and implications of EIT in future communication systems
● Impact of the interconnect on application performance, and evaluation thereof
● Thermal-/energy-and power-related NoC optimization and dark silicon
● Reconfigurable/programmable interconnect components
● 2.5D and 3D packaging concerns for interconnects
● Asynchronous interconnect designs
● Clockless interconnects with focus on automation of their design methodology
● Network infrastructures for Internet-of-Things devices
● Network solutions for performance isolation in many-core systems
● Reliability, availability, fault tolerance for system communication
● Programming models for communication-centric systems
● Secure interconnection networks for intra-chip and inter-chip communication

WORKSHOP WEBSITE
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http://mpsoc.unife.it/~aistecs/

SUBMISSION PROCESS
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Submission website: https://easychair.org/conferences/?conf=aistecs20170

Papers with up to 4 pages (A4) must be submitted in PDF format and should include title, authors, affiliations and corresponding author email. Papers must be formatted in accordance to the ACM two-column style. ACM Word or LaTeX style templates will be available on the website. Papers deviating significantly from the paper size and formatting rules may be rejected without review. Each paper will be peer-reviewed by at least 3 reviewers. The submission and review process will be handled electronically via EasyChair: https://easychair.org/conferences/?conf=aistecs20170

PUBLICATION
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(To be confirmed) Accepted papers will be published in the ACM Digital Library within the ACM International Conference Proceedings Series (ICPS). Authors will be sent the ACM form and instructions to finalize the camera-ready submission and to complete the publication procedure.

REGISTRATION
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At least one registration is required per accepted paper, and one author is expected to present the paper at the workshop. Registration will be handled via the HiPEAC Conference.

WORKSHOP ORGANIZERS
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GENERAL CHAIRS:
● Sören Sonntag, Intel, Germany
● José Manuel García Carrasco, University of Murcia, Spain

PROGRAM CHAIRS:
● Sébastien Rumley, Columbia University, USA
● Alessandro Cilardo, University of Naples Federico II, Italy

STEERING COMMITTEE:
● Davide Bertozzi, University of Ferrara, Italy
● Cyriel Minkenberg, Rockley Photonics, USA

TECHNICAL PROGRAM COMMITTEE
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● José Luis Abellan Miguel, Catholic University of Murcia, Spain
● Federico Angiolini, EPFL, Switzerland
● Luca Alloatti, ETH, Switzerland
● Sandro Bartolini, University of Siena, Italy
● Giorgos Dimitrakopoulos, Democritus University of Thrace, Greece
● José Flich, University of Valencia, Spain
● Holger Fröning, University of Heidelberg, Germany
● Edoardo Fusella, University of Naples Federico II, Italy
● John Kim, KAIST, South Korea
● George Michelogiannakis, Lawrence Berkeley National Laboratory, USA
● Sergei Mingaleev, VPIphotonics, Germany
● Daniel Müller-Gritschneder, TU Munich, Germany
● Mahdi Nikdast, Colorado State University, USA
● Nikos Pleros, Aristotle University of Thessaloniki, Greece
● José Luis Sanchez Garcia, University of Castilla-La Mancha, Spain
● Laurent Schares, IBM Watson, USA
● Ashkan Seyedi, HPE, USA
● Federico Silla, University of Valencia, Spain
● Yvain Thonnart, CEA-Leti, France