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IA^ 2017 : Seventh Workshop on Irregular Applications: Architectures and Algorithms

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Link: http://hpc.pnl.gov/IA3/
 
When Nov 13, 2017 - Nov 13, 2017
Where Denver
Abstract Registration Due Aug 22, 2017
Submission Deadline Aug 29, 2017
Notification Due Oct 3, 2017
Final Version Due Oct 10, 2017
Categories    computer science   graph algorithms   HPC   computer architecture
 

Call For Papers

IA^3 2017
Seventh Workshop on Irregular Applications: Architectures and Algorithms
http://hpc.pnl.gov/IA3/
November 13, 2017
In conjunction with SC17
In collaboration with ACM SIGHPC
Sponsored by IEEE TCHPC

Call for Papers

Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, tables, sparse matrices, deep nets, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:

* Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors
* Network architectures and interconnect (including high-radix networks, optical interconnects)
* Novel memory architectures and designs (including processors-in memory)
* Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing)
* Modeling, simulation and evaluation of novel architectures with irregular workloads
* Innovative algorithmic techniques
* Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
* Impact of irregularity on machine learning approaches
* Parallelization techniques and data structures for irregular workloads
* Data structures combining regular and irregular computations (e.g., attributed graphs)
* Approaches for managing massive unstructured datasets (including streaming data)
* Languages and programming models for irregular workloads
* Library and runtime support for irregular workloads
* Compiler and analysis techniques for irregular workloads
* High performance data analytics applications, including graph databases

Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.

Artifact Evaluation

For this edition of IA3, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation process, similarly to the process followed for SC17. The participation to the Artifact Evaluation process is voluntary and will not change decisions regarding the paper. However, papers that undergo the evaluation process will receive a seal of approval on the paper, and will be able to participate in the BEST PAPER AWARD selection. DIVIDITI will provide an Amazon Gift Voucher (valued $200) to the authors of the paper that passes artifact evaluation with the highest score and that shares the artifact in the CK (Collective Knowledge - https://github.com/ctuning/ck) format. Authors that go through the Artifact Evaluation process are also encouraged (but not mandated) to submit the supporting materials as “Source Materials” in the digital library. For details on how to submit supporting materials to the Artifact Evaluation process, please refer to: http://ctuning.org/ae/submission.html.

For any additional question on the Artifact Evaluation process please contact the Artifact Evaluation Chair Flavio Vella.

Important Dates

Abstract submission: 22 August 2017
Position or full paper submission: 29 August 2017
Notification of acceptance: 3 October 2017
Camera-ready position and full papers: 10 October 2017
Workshop: 13 November 2017

Submissions

Submission site: https://easychair.org/conferences/?conf=ia32017

All submissions should be in double-column, single-spaced letter format, with at least one-inch margins on each side and respect the ACM standard proceedings templates (sigconf) available at: https://www.acm.org/publications/proceedings-template.
The proceedings of the workshop will be published in cooperation with ACM SIGHPC.
Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four(4) pages for position papers including figures, tables and references.


Organizers

Antonino Tumeo, PNNL, US
John Feo, PNNL/NIAC, US,
Vito Giovanni Castellana, PNNL, US

Artifact Evaluation Chair

Flavio Vella, DIVIDITI, UK

Publication Chair

Marco Minutoli, PNNL, US

Program Committee

Scott Beamer, LBNL, US
Michela Becchi, North Carolina State University, US
Erik Boman, Sandia National Laboratories, US
David Brooks, Harvard University, US
Aydin Buluc, LBNL, US
Sunita Chandrasekaran, University of Delaware, US
Fabio Checconi, IBM, US
Rajiv Gupta, Univerisity of California Riverside, US
Maya Gokhale, LLNL, US
Peter Kogge, Univ. of Notre Dame, US
Vivek Kumar, Rice University, US
John Leidel, Texas Tech University, US
Kamesh Madduri, Pennsylvania State University, US
Naoya Maruyama, RIKEN AICS, JP
Tim Mattson, Intel, US
Miquel Moreto, BSC and UPC, SP
Richard Murphy, Micron Technology Inc, US
Walid Najjar, University of California Riverside, US
Maxim Naumov, NVIDIA, US
Jacob Nelson, University of Washington, US
Sreepathi Pai, University of Rochester, US
Roger Pearce, LLNL, US
Miquel Pericas, Chalmers University, SE
Viktor Prasanna, University Of Southern California, US
Alejandro Rico, ARM, US
Jason Riedy, Georgia Institute of Technology, US
Erik Saule, University of North Carolina at Charlotte, US
John Shalf, LBNL, US
Shaden Smith, University of Minnesota, US
Bora Ucar, CNRS and LIP ENS Lyon, FR
Ruud Van Der Pas, Oracle, US
Flavio Vella, DIVIDITI, UK
Ana Lucia Varbanescu, University of Amsterdam, NL

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