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VLSI 2017 : Free VLSI Workshop for Working Professionals!!!

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Link: https://docs.google.com/a/aceic.com/forms/d/e/1FAIpQLSfzBg_1zGQVG4pVCPbgVYmDLMV-D1E6QfBO39zWiTNDd4XxBQ/viewform
 
When Apr 22, 2017 - Apr 22, 2017
Where M​aven Silicon
Submission Deadline Apr 21, 2017
Categories    VLSI   UVM   system verilog
 

Call For Papers

Do you want to upgrade your Skills and survive in the VLSI World??

Then join us for an Impactful FREE Workshop on ASIC Verification and get a chance to interact with Mr. Sivakumar PR, a seasoned engineering professional with a rich experience of over 19 years, a well known name in the VLSI fraternity.

Ask questions, seek answers, bust the myths, go back home reflecting on the latest verification trends you can easily adopt!

Block the date:22/April/2017

Time : 9 AM to 1 PM

Agenda :
· Verification Methodology
· Reusable TB
· CRCDV - Directed Vs Random
· Why SystemVerilog?
· Overview of UVM
· Case Study: ABLE5 - Aceic's Bluetooth LE VIP
· Technical Quiz and Gifts

Venue :​
M​aven Silicon
# 21/1A, III Floor, Marudhar Avenue,
Gottigere, Uttarahalli Hobli, South Taluk,
Bannerghatta Road, Bangalore - 560076


Limited Seats!!
Click Here ​To Register::
https://docs.google.com/a/aceic.com/forms/d/e/1FAIpQLSfzBg_1zGQVG4pVCPbgVYmDLMV-D1E6QfBO39zWiTNDd4XxBQ/viewform

For more details​ ​​c​ontact us​:​

📞+91​-​ 9148637555 ​/ ​​📝 corporate@maven-silicon.com

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