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HCPM 2017 : Workshop on HPC Computing in a Post Moore's Law World 2017


When Jun 22, 2017 - Jun 22, 2017
Where Frankfurt, Germany
Submission Deadline Mar 19, 2017
Notification Due Apr 10, 2017
Categories    HPC   moore's law   devices   architecture

Call For Papers

Thursday June 22nd, 2017, Frankfurt, Germany
Held in conjunction with ISC 2017


HPCM aims to discuss potential strategies, opportunities, and challenges for supercomputing beyond the scaling limits of Moore’s Law. Due to the multidisciplinary nature of this problem, formulating a strategy is likely to require a comprehensive re-thinking of technologies, ranging from innovative materials and devices, circuits, system architectures, programming systems, system software, and applications. HPCM will feature paper presentations, keynote addresses, and short panels to foster foster interdisciplinary dialog across the necessary spectrum of stakeholders: applications, algorithms, software, and hardware, from academia and industry alike. Many important questions need to be addressed, such as what technologies are the most promising candidates for the future, the impact to the software layer such as applications, algorithms compilers and programming models, impact to the architectures such as interconnects, parallelism, and the memory hierarchy, as well as challenges in modeling and simulation of future architectures. However, this list is by no means an exhaustive list of questions.


Submission deadline: Monday March 19th 2017, anywhere on earth (AOE). Extended from March 6th.
Notification: Monday April 10th 2017.


This list is not exhaustive. Any topic relevant to the future of HPC as tied to the future of Moore's law is relevant.

- Optics and photonics, to include communication, switching, and other emerging topics.
- Neuromorphic computing. Its current state, as well as future trends for performance and applicable application domains.
- Quantum computing. Manufacturability, feasibility, application domains, as well as current implementations.
- Superconducting circuits.
- Novel device technologies that conform to the digital computing model, such as tunnel FETs, negative capacitance FETs, and carbon nanotube FETs.
- Novel memory technologies such as resistive RAM, magnetic RAM and other volatile and nonvolatile options.
- 3D integration. Future capabilities in terms of number of layers, types of layers (memory versus logic), as well as challenges such as heat density.
- Impact of new technologies to the architecture, to include interconnect, memory hierarchy (such as caches), parallelism, ISA choice, etc.
- Inexact computing such as approximate computing. What kinds of applications can tolerate errors, and how to use this strategy to mitigate technology problems.
- Identifying the main application drivers for increased performance.
- Modeling and evaluation of novel technologies.
- Software impact of novel technologies, to include programmability, application algorithms, compilation, run-time systems, and other topics.
- Funding opportunities for research in this field.


The website contains more detailed instructions as well as committee/contact information.


Submission website:

Papers need to be formatted according to Springer’s single column LNCS style (see this link for LaTeX and Word templates). Papers are limited to 8 pages including figures, references, the abstract, and everything else. Selected papers will be published in ISC’s 2017 workshop proceedings with Springer. Authors will have a chance to revise their papers according to feedback they receive during the workshop and submit a camera-ready version by July 22nd 2017. The review process will be single-blind.

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