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DSC 2017 : 2017 IEEE Conference on Dependable and Secure Computing


When Aug 7, 2017 - Aug 10, 2017
Where Taipei, Taiwan
Abstract Registration Due Mar 25, 2017
Submission Deadline Mar 31, 2017
Notification Due May 10, 2017
Final Version Due May 28, 2017
Categories    security   dependability   systems   hardware

Call For Papers

[Apologies for multiple copies.
Appreciated if you can forward to potentially interested persons. ]

DSC 2017
2017 IEEE Conference on Dependable and Secure Computing
Taipei, Taiwan | August 7--10, 2017


The IEEE Conference on Dependable and Secure Computing solicits papers,
posters, practices, and experiences for presenting innovative research
results, problem solutions, and new challenges in the field of dependable and
secure computing. The whole spectrum of IT systems and application areas,
including hardware design and software systems, with stringent relevant to
dependability and security concerns are of interest to DSC. Authors are
invited to submit original works on research and practice of creating,
validating, deploying, and maintaining dependable and secure systems. The
scope of DSC includes, but is not limited to, the following topics:

** Track #1: Computer Systems, Networks, and Software

- Advanced Persistent Threat (APT)
- Big Data Analysis
- Botnet and Intrusion Detection
- Cryptographic Methods and Toolkits
- Cyber attacks
- Data/Information Reliability
- Database Security and Privacy
- Embedded Systems and IoT Devices
- Experimentation, Measurement, and Assessment
- Mobile and Cloud Computing
- SDN and NFV

** Track #2: System Electronics, VLSI, and CAD

- CAD Algorithms and Tools
- Electronic Circuits and Systems
- Fault-Tolerant Architectures and Designs
- Industrial Design Experiences
- Noise-Aware Designs
- Power-Aware Designs
- Soft-Error Analysis and Models
- Stochastic Circuits and Systems
- Temperature-Aware Designs
- Variable-Latency Designs
- Security Circuits, Designs and Detection

** Track #3: Experience and Practice

The DSC conference will also include a submission category for experience
and practice papers on new findings in the two aforementioned categories.
The PC will evaluate a submission to the experience and practice track with
the understanding that it predominantly contributes to the VLSI/CAD design
knowhow or the extension of the community's knowledge about how the
security protection of known techniques fares in real-world operations.
Authors have to submit a short paper along with slides and an optional
supplemental video to demonstrate the implementation and/or the
practicability of the work. Topics of interest include, but are not limited

- Attacks on Information Systems and Digital Storage
- CSIRTs, Incident Analysis and Response
- Hacking Techniques and Countermeasures
- Honeypots/Honeynets
- Malware Analysis and Reversing
- Mobile Communications Security and Vulnerabilities
- Newly discovered vulnerabilities
- Offensive Information Technology
- Reverse Engineering, Forensics, and Anti-Forensics
- Spyware, Phishing and Distributed Attacks
- VLSI/CAD Design Knowhow

Manuscript Format

Papers should describe the original work with focus details. It should be no
more than 8 pages for regular papers and 2 pages for experience and practice
papers. Each submission will only be considered for one track - either the
main conference tracks or the experience track, but not both. Papers must be
written in English conforming to the IEEE standard conference format (US
letter, two-column). All submitted papers will be peer-reviewed. Accepted
papers will appear in the conference proceedings and will be included in the
IEEE Xplore digital library. Authros of selected papers will be invited to
submit enhanced versions to IEEE Reliability magazine and journals.

Important Dates (**updated)

- Abstract submission due: March 25, 2017
- Paper submission due: March 31, 2017
- Notification of paper acceptance: May 10, 2017
- Workshop paper/poster submission due: May 17, 2017
- Notification of workshop paper/poster acceptance: May 24, 2017
- Camera ready: May 28, 2017


** Honorary Chair
- Der-Tsai Lee Academia Sinica, Taiwan

** General Chairs
- Wen-Guey Tzeng National Chiao Tung University, Taiwan
- Luc Claesen University Hasselt, Belgium

** Program Chairs
[Computer Systems, Networks, and Software]
- Doug Tygar University of California, Berkeley, USA
- Chun-Ying Huang National Chiao Tung University, Taiwan
[System Electronics, VLSI, and CAD]
- Bevan Baas University of California, Davis, USA
- Terngyin Hsu National Chiao Tung University, Taiwan
[Experience and Practice]
- Tzi-Cker Chiueh Idustrial Technology Research Institute, Taiwan
- Fu-Hau Hsu National Central University, Taiwan

** Workshop Chair
- Chi-Yu Li National Chiao Tung University, Taiwan

** Publicity Chairs
- Morris Chang University of South Florida, USA
- D.J. Guan National Sun Yat-sen University, Taiwan
- Xinyi Huang Fujian Normal University, China

** Publication Chair
- Chi-Wei Yi National Chiao Tung University, Taiwan

** Financial Chair
- Yu-Sung Wu National Chiao Tung University, Taiwan

** Local Arrangement Chair
- Shih-Kun Huang National Chiao Tung University, Taiwan

** Steering Committee
- David Basin ETH Zurich, Switzerland
- Robert Deng SMU, Singapore
- Jerry Shyh-Jye Jou National Chiao Tung University
- Chen-Yi Lee National Chiao Tung University
- Shiuhpyng Winston Shieh National Chiao Tung University
- Doug Tygar University of California, Berkeley, USA

[ For more information, please check the conference website at ]

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