posted by user: yoshiki || 1779 views || tracked by 10 users: [display]

HEART 2017 : International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

FacebookTwitterLinkedInGoogle

Link: http://www.isheart.org/HEART2017
 
When Jun 6, 2017 - Jun 9, 2017
Where Bochum, Germany
Submission Deadline Mar 19, 2017
Notification Due Apr 15, 2017
Final Version Due Apr 30, 2017
Categories    GPGPU   FPGA   custom computing system   run-time techniques
 

Call For Papers

========================================================================
HEART-2017 DEADLINE HAS BEEN EXTENDED TO MARCH 19 (Firm deadline).
========================================================================

/****************************************************************/

Call for Papers
Abstract Submission Deadline: March 15th, 2017
Full Paper Submission Deadline: March 19th, 2017 (Firm Deadline)

Call for Design Competitions
Design Competition Paper submission: March 31, 2017

The 8th International Symposium on
Highly Efficient Accelerators and Reconfigurable Technologies
(HEART2017)

7-9 June 2017, Bochum, Germany
(http://heart2017.esit.rub.de/) http://heart2017.esit.rub.de/

/****************************************************************/

Important dates:
- Submission deadline for abstracts of conference papers: March 15, 2017
- Submission deadline for full conference papers: March 19, 2017 (Firm deadline)
- Submission deadline for design competition papers: March 31, 2017
- Acceptance notification: April 15, 2017
- Camera-ready/Author registration: April 30, 2017
- Symposium dates: June 7-9, 2017

/****************************************************************/

Highlights:
- Xilinx Pynq Workshop will be organized on June 6, 2017
- Social Event: Starlight Express Musical

/****************************************************************/

The 8th International Symposium on Highly Efficient Accelerators and
Reconfigurable Technologies (HEART) is a forum to present and discuss new
research on accelerators and the use of reconfigurable technologies for
high-performance and/or power-efficient computation. Submissions are
solicited on a wide variety of topics related to the acceleration for
high-performance computation, including but not limited to:

- Architectures and systems:
--- Novel systems/platforms for efficient acceleration based on FPGA, GPU,
and other devices

--- Heterogeneous processor architectures and systems for scalable,
high-performance, high-reliability, and/or low-power computation

--- Reconfigurable and configurable hardware and systems including IP-cores,
embedded systems, SoCs, and cluster/grid/cloud computing systems for
scalable, high-performance and/or low-power processing

--- Custom computing system for domain-specific applications such as
Big-data, multimedia, bioinformatics, cryptography, and more

--- Novel architectures and device technologies that can be applied to
efficient acceleration, including many-core/NoC architectures, 3D-stacking
technologies and optical devices

- Software and applications:
--- Novel applications of high-performance computing and Big-data processing
with efficientacceleration and custom computing

--- System software, compilers and programming languages for efficient
accelerationsystems / platforms, including many-core processors, GPUs, FPGAs
and otherreconfigurable /custom processors

--- Run-time techniques for acceleration, including Just-in-Time compilation
and dynamicpartial-reconfiguration

--- Performance evaluation and analysis for efficient acceleration

--- High-level synthesis and design methodologies for heterogeneous,
reconfigurable and/orcustom processors/systems

In order to encourage open discussion on future directions, the program
committee will provide higher priority for papers that present highly
innovative and challenging ideas.

We are planning to organize special sessions on HPC, Big data, and Dynamic
Reconfiguration. When submitting a paper, please select
topic(s) if the paper is related to them. Note that regardless of the
selection of special session topic(s), your paper will undergo the same
peer-review process as the main technical track.

Prospective authors are invited to submit original and unpublished
contributions as 6-page papers to be considered as regular papers or 4-page
papers to be considered as poster papers. All contributions must be
submitted electronically in PDF format (two columns, US letter size,
single-spacing, 10 points for main body text).

For double-blind review, manuscripts must NOT identify the authors in any
way, so author names, affiliations, e-mail addresses and self-references
should be blanked out. Papers that identify authors may be rejected without
review. You can submit your contribution(s) by following this easychair
submission link.

Submission: (https://www.easychair.org/conferences/?conf=heart2017) https://www.easychair.org/conferences/?conf=heart2017

Each accepted paper MUST have at least one author with a regular
registration for the manuscript to be included and published in the
symposium proceedings and ACM post-proceedings (tentative).
Authors are also expected to attend and present their paper(s) at the
symposium.

The HEART2017 paper template can be download here: HEART2017 template in
MS-Word, HEART2017 template in Latex.
MS-Word: (http://www.isheart.org/HEART2017/heart2017.doc) http://www.isheart.org/HEART2017/heart2017.doc
Latex: (http://www.isheart.org/HEART2017/heart2017.cls) http://www.isheart.org/HEART2017/heart2017.cls
------------------------------------------------------------------------

Organizing Committee:

General co-chairs:
Diana Goehringer, Ruhr-University Bochum, DE
Michael Huebner, Ruhr-University Bochum, DE

Technical program co-chairs:
Holger Blume, Leibniz University Hannover, DE
Martin Herbordt, Boston University, US
Hiroki Nakahara, Tokyo Tech, JP

Publicity co-chairs:
Kenji Kanazawa, University of Tsukuba, JP
Gabriel Marchesan, Harman International, DE
Brain Veale, IBM, US

Finance and local arrangement chair:
Linda Trogant, Ruhr-University Bochum, DE

Publication chair:
Yuichiro Shibata, Nagasaki University, JP

Design contest chair:
Donald Bailey, Donald Bailey, NZ

_______________________________________________

Related Resources

FCCM 2018   26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018)
NSDI 2017   14th USENIX Symposium on Networked Systems Design and Implementation
ReCoSoC 2018   13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip
NAACL HLT 2018   The 16th Annual Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies
ASAP 2017   Application-Specific Systems, Architectures, and Processors
ARC 2018   14th International Symposium on Applied Reconfigurable Computing
EfficientConvNets 2017   Challenge on Efficient ConvNets for Semantic Segmentation
IEEE ISNCC 2018   2018 IEEE International Symposium on Networks, Computers and Communications
EI CAECT 2018   2018 International Conference on Aerospace Engineering and Control Technologies(CAECT 2018)
WINCOM 2017   THE INTERNATIONAL CONFERENCE ON WIRELESS NETWORKS AND MOBILE COMMUNICATIONS