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PACT 2017 : International Conference on Parallel Architectures and Compilation Techniques


Conference Series : International Conference on Parallel Architectures and Compilation Techniques
When Sep 13, 2017 - Sep 17, 2017
Where Portland, Oregon, USA
Submission Deadline Mar 14, 2017
Notification Due May 24, 2017
Final Version Due Jul 19, 2017
Categories    computer architecture   compilers   parallel computing

Call For Papers


26th International Conference on Parallel Architectures & Compilation Techniques

September 9-13, 2017 Portland, Oregon, USA


The purpose of PACT 2017 is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest.

PACT started as a Data Flow Workshop in conjunction with ISCA 1989 but quickly evolved into a unique venue at the intersection of classical parallel architecture and compilers.

Recently, PACT widened its scope to include insights useful for the design of machines and compilers from applications such as, but not limited to, machine learning, data analytics and computational biology.

PACT solicits novel papers, workshops, tutorials, and entries to an ACM student research competition on a broad range of topics that include, but are not limited to:

o Parallel architectures and computational models
o Compilers and tools for parallel computer systems
o Multicore, multithreaded, superscalar, and VLIW architectures
o Compiler/hardware support for hiding memory latencies
o Support for correctness in hardware and software
o Reconfigurable parallel computing
o Dynamic translation and optimization
o I/O issues in parallel computing and their relation to applications
o Parallel programming languages, algorithms and applications
o Middleware and run time system support for parallel computing
o Application-specific parallel systems
o Applications and experimental systems studies of parallel processing
o Relevant aspects of distributed computing and mobile computing
o Heterogeneous systems using various types of accelerators
o Insights from modern parallel applications such as, but not limited to,
machine learning, data analytics, and computational biology for the design
of parallel architectures and compilers


Paper Deadline....................March 14, 2017
Author Response Period........May 3-6, 2017
Author Notification...............May 24, 2017
Camera Ready Final Papers...July 19, 2017


Submitted papers will be evaluated on technical merits and clarity of presentation. Papers must contain sufficient information and be organized in such a way that their technical contribution and significance can be understood by a wide audience of computer scientists.

Submitted papers must be original material that has not been previously published in another conference or journal, nor is currently under review by another conference or journal. Papers are to be submitted for double-blind review. This means that author names as well as hints of identity are to be removed from the submitted paper.

Authors of accepted papers will be invited to formally submit their supporting materials to the Artifact Evaluation Committee. The task of this committee is to assess how the artifacts support the work described in the papers. Submission is volunta ry. Papers that go through the artifact evaluation process successfully will receive a seal of approval which will be printed on the first page of the papers in the proceedings.


General Chair: Ravi Iyer, Intel
Program Chair: David Padua, University of Illinois


ACM, IEEE Computer Society

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