posted by user: rbertra || 723 views || tracked by 2 users: [display]



When Feb 4, 2017 - Feb 4, 2017
Where Austinx, TX, USA
Submission Deadline Dec 4, 2016
Notification Due Dec 18, 2016
Final Version Due Jan 8, 2017
Categories    computer architecture   microarchitecture    compiler   circuit design

Call For Papers

Call for Contributions - WP3 - 2016
in conjunction with the 23rd IEEE Symposium on High
Performance Computer Architecture (HPCA'16)
4 February, 2017 / Austin, TX, USA

Innovations in instruction set architecture (ISA),
processor microarchitecture and supportive advances in
circuit design, compilers, semiconductor technology,
pre-silicon specification, modeling and validation
have all been essential elements of the computer
systems revolution that has transformed human society
so dramatically over the last six decades or more.
In the late CMOS era, with power and reliability walls
already causing major paradigm shifts, the need for
new innovations in cross-layer, hardware-software
design and modeling are being called for to help
keep the IT industry moving and growing at historical

In trying to forge a path of innovation, it is sometimes
worth examining the past to look for major paradigm
shifts in (micro)-architecture, circuits, modeling
and software that helped us keep going in the face
of past technology-driven disruption points. With
this in mind, we present a new workshop pioneering
processor paradigms (P3). With the help of true
pioneers as well as budding new researchers, P3 will
take a retrospective look at how past technological
hurdles were circumvented through major innovations.
The goal is to learn from the past in devising new
solution strategies for the future.

The P3 workshop will offer a number of invited talks
from true pioneers as well as reviewed selections
from the new generation of researchers and teachers
who are eager to take a retrospective look into
surveying past pioneering work that can teach us a
lesson about solution strategies of the future.

*** Important Dates:

- Submission deadline: December 4, 2016
- Notification of acceptance: December 18, 2016
- Final paper submission: January 8, 2017
- Workshop date: February 4, 2017

** Call for contributions

The workshop on pioneering processor paradigms invites
survey (or tutorial)-like submissions for review. The
ideal paper would highlight a single pioneering paper
(or set of papers) constituting a major processing,
design, modeling or software paradigm shift in the past.
In addition to explaining the context and basic concepts
articulated in such work, the author(s) should draw
relevant conclusions about how this pioneering work
could or should influence computing paradigms of the

Note: Ph.D dissertation research topic proposals from
(junior graduate students) that contain a survey of a
key paper or two to build up the motivational justification
of the proposal are quite welcome, for example.

** Topics of interestest

Example topic areas include (but are not limited to):

- Processing and cache taxonomy papers.
- RISC architectures and CISC-to-RISC dynamic translation
- Processor pipelining, super scalar processing and
branch prediction innovations.
- Register renaming, out-of-order execution and precise
- Cycle-accurate processor performance modeling.
- Innovations in floating point arithmetic units and
vector/SIMD acceleration.
- VLIW architectures.
- Multi-threading, multiscalar and speculative multi-threading.
- Homogeneous and heterogeneous multi-core processors;
accelerator-enabled efficiency boost.
- Power, temperature, and reliability-aware computing –
with associated modeling innovations.
- Compiler innovations in support of novel microarchitectural
- Circuit design innovations in support of (micro)-architectural
paradigm shifts.

*** Registration
Refer to main conference:

*** Hotel Reservation
Refer to main conference:

For more details, please see

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