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JEDT 2017 : International Journal of Electronic Design and Test

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Link: http://airccse.com/jedt/index.html
 
When N/A
Where N/A
Submission Deadline May 31, 2017
Notification Due Jun 30, 2017
Final Version Due Jul 10, 2017
Categories    VLSI   simulation   design   circuits
 

Call For Papers

International Journal of Electronic Design and Test(JEDT)


Call for Papers


International Journal of Electronic Design and Test(JEDT) is a peer-reviewed, open access journal which invites original works describing the methods used to design and test electronic product hardware and supportive software. Authors from industry and academia are invited to submit their original unpublished research works on the topics listed below:


Topics of Interest


  • IC/module design
  • Low-power design
  • Electronic design automation
  • Design/test verification
  • Fault modelling
  • Test generation
  • Fault simulation
  • Design of testability
  • Synthesis of testability
  • Built-in self-test
  • Test specifications
  • Formal verification of hardware
  • Simulation for verification
  • Design debugging
  • Testing of VLSI devices printed circuit boards, and electronic systems
  • Testing of analog and digital electronic circuits
  • Testing of microprocessors, memories and signal processing devices
  • SOC and SIP testing
  • Memory and FPGA test and repair
  • Delay testing
  • IDDQ test
  • Novel test methods
  • Effectiveness of test methods
  • Fault models and ATPG, and DPPM prediction
  • DFT for analog/mixed signal ICs and system-on-chip
  • DFT and BIST for digital and SoC

Paper Submission


Authors are invited to submit papers for this journal through E-mail: jedtjournal@airccse.com . Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.


Important Dates

 


Submission Deadline:May 31, 2017
Authors Notification:June 30, 2017
Final Manuscript Due:July 10, 2017
Publication Date:Determined by the Editor-in-Chief

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