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PDAA 2016 : PDAA 2016: The 8th International Workshop on Parallel and Distributed Algorithms and Applications


When Nov 22, 2016 - Nov 25, 2016
Where Hiroshima, Japan
Abstract Registration Due Aug 14, 2016
Submission Deadline Aug 18, 2016
Notification Due Sep 10, 2016
Final Version Due Sep 23, 2016
Categories    parallel processing   distributed computing   applications   algorithms

Call For Papers


The 8th International Workshop on Parallel and Distributed Algorithms and
Applications (PDAA'16)

To be held in conjunction with
CANDAR'16, Hiroshima, Japan, November 22-15, 2016

[Bridging Theory and Practice in Parallel and Distributed Computing]

The main goal of this workshop is to provide a timely forum for the
exchange and dissemination of new ideas, techniques and research in
the field of parallel and distributed algorithms and applications. The
workshop is meant to bridge research of theory and practice in all
aspects of parallel and distributed computing. We are convinced that
the workshop atmosphere will be conducive to open and mutually
beneficial exchanges of ideas between the participants of these areas.

[Topics of interest include, but are not limited to]

* Theory and Algorithms
Parallel and distributed algorithms, Hardware algorithms,
Graph-theoretic concepts in parallel and distributed computing,
Geometric and graph algorithms, Complexity theory in parallel and
distributed computing, Parallel and distributed computing models,
Network routing and communication algorithms, Combinatorial
algorithms, Randomized and approximation techniques, Cellular Automata

* Parallel and Distributed Computing
DNA Computing, Membrane Computing, Quantum Computing, Internet
Computing, Wireless networks and mobile computing, Internet computing,
Reconfigurable Computing, Internet Computing, Optical Computing

* Practical Aspects and Applications
Parallel computing systems, Supercomputing, Cluster computing, Grid
Computing, Parallel/distributed architectures, P-to-P networks,
Performance analysis and simulation, PVM/MPI, CUDA/GPGPU, Multi-core
processors, Programmable logic arrays, Reconfigurable Architectures,
Image Processing, Security Issues

[Paper format]

- Regular paper: 5-7 pages
- Poster paper: 3-4 pages

[Submission Instruction]

Please see Workshop Paper Submission Instruction.


The conference and workshop proceedings will be published by
Conference Publishing Service and submitted to IEEE Xplore and CSDL
digital libraries. Also they are submitted for indexing through
INSPEC, EI (Compendex), Thomson ISI, and other indexing services.

[Special Issue]

We plan to publish extended versions of selected papers from CANDAR
main symposium and workshops in IEICE Transactions on Information
and Systems (IEICE-ED) and in International Journal of Networking and

[Important dates]

* Abstract submission: August 14, 2016 (extended)
* Paper submission: August 18, 2016 (extended)
* Notification of paper acceptance: September 10, 2016
* Submission of camera-ready papers: September 23, 2016


* Workshop chair
- Susumu Matsumae (Saga University)

* Program Committee
- Antoine Bossard (Kanagawa University)
- Akihiro Fujiwara (Kyushu Institute of Technology)
- Yasuaki Ito (Hiroshima University)
- Chuzo Iwamoto (Hiroshima University)
- Taisuke Izumi (Nagoya Institute of Technology)
- Xiaohong Jiang (Future University Hakodate)
- Hirotsugu Kakugawa (Osaka University)
- Sayaka Kamei (Hiroshima University)
- Guoqiang Li (Shanghai Jiao Tong University)
- Yamin Li (Hosei University)
- Jaime Lloret (Polytechnic University of Valencia)
- Eiji Miyano (Kyushu Institute of Technology)
- Takayuki Nagoya (Tottori University of Environmental Studies)
- Fukuhito Ooshita (NAIST)
- Wei Sun (Data61/CSIRO)
- Yasuhiko Takenaga (The University of Electro-Communications)
- Jerry Trahan (Louisiana State University, Baton Rouge)
- Shinichi Yamagiwa (University of Tsukuba)
- Yukiko Yamauchi (Kyushu University)

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