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IXPUG-ISC 2016 : IXPUG-ISC16 Workshop Application Performance on Intel Xeon Phi – Being Prepared for KNL and Beyond


When Jun 23, 2016 - Jun 23, 2016
Where Frankfurt (Main), Germany
Abstract Registration Due Apr 15, 2016
Submission Deadline Apr 22, 2016
Notification Due May 27, 2016
Final Version Due Jun 30, 2016
Categories    computer science   HPC   many-core computing   intel xeon phi

Call For Papers

Many-core and multicore processor technologies have put more demand on memory and interconnects. These processor technologies also require a more detailed understanding of the interaction between the memory, interconnect and SIMD units for users to design optimal algorithms at scale on a node, as well as at scale on a system level.

The IXPUG workshop is about sharing ideas, implementations, and experiences that will help users take advantage of new technologies such as AVX512 operations, high-bandwidth memory (HBM) and OmniPath. These architectural advances in Vectorization, Memory, and Communications on the Intel Xeon Phi platform will help boost adoption of many-core architecture in HPC as well as other computational spaces.

In the workshop you will experience an open forum with fellow application programmers, Intel Phi architecture designers, and compiler and tool experts.

In addition to the technical paper presentations, the program will include a morning keynote on Intel microprocessors and an afternoon presentation on memory performance, and will conclude with a panel discussion.

IXPUG welcomes paper submissions on innovative work from KNC and KNL users in academia, industry and government labs, describing original discoveries and experiences that will promote and prescribe efficient use of many-core and multicore systems.

Topics of interest are (but not limited to):
- Vectorization: Data layout in cache for efficient SIMD operations, SIMD directives and operations, and 2-core tiling with 2D interconnected mesh

- Memory: Data layout in memory for efficient access (data preconditioning), access latency concerns (prefetch, streams, costs for HBM), partitioning of DDR and HBM for applications (memory policies)

- Communication, including early experiences with OmniPath

- Thread and Process Management: Process and thread affinity issues, SMT (simultaneous multi-threading, in core), balancing processes and threads

- Programming Modells: OpenMP 4.x, hStreams, using MPI 3 on Xeon Phi, hybrid programming (MPI/OpenMP, others)

- Algorithms and Methods: , including scalable and vectorizable algorithms

- Software Environments and Tools

- Benchmarking & Profiling Tools

- Visualization

See website for information for authors and submission format.

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