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PPEO 2016 : International Workshop on Performance, Power and Energy-Efficiency Optimization in Heterogeneous Systems


When Jul 1, 2016 - Jul 1, 2016
Where Porto, Portugal
Abstract Registration Due Mar 27, 2016
Submission Deadline Apr 3, 2016
Notification Due May 1, 2016
Final Version Due May 15, 2016
Categories    high performance computing   computer architecture   FPGA   embedded systems

Call For Papers

To satisfy the growing demands for higher application performance and reduced power and energy consumption, parallel and heterogeneous computing systems have gradually become a prevailing solution. As a result, performance and energy efficiency optimization has become a fundamental constraint and requisite, embracing the processor architectures (homogeneous/heterogeneous many-core GPPs), the accelerators and co-processors (e.g., APUs, GPUs, FPGAs, etc.), and even the embedded domain (e.g., ARM big.LITTLE), where the development of energy saving methodologies is a fundamental issue for mobile, hand-held and wireless applications.

The need to satisfy the required performance levels, allied with new thermal, power and energy constraints require innovative solutions to attain an effective optimization of the offered throughput and/or minimization of the power/energy consumption. Among many other research directions, this challenge naturally involves the design of high performance and energy-efficient architectures and communication infrastructures, as well as the development of novel algorithms and tools comprising the scheduling, mapping, load-balancing and scalability, together with innovative compilation techniques.

The goal of this workshop is to bring together active researchers who are interested in prevailing issues and prominent challenges related to optimizing the performance, power, and energy efficiency in the latest generations of heterogeneous computing devices and systems.

The PPEO Workshop topics of interest include (but are not limited to) the following:

- Heterogeneous and parallel processing architectures;
- ISA diversity and morphable structures;
- Run-time reconfiguration/adaptation and dynamic scalability;
- CPU accelerator co-design (GPUs, APUs, FPGAs, etc.);
- Approximate computing techniques and architectures;
- Neuromorphic architectures.

- Run-time power/energy monitoring and sensing;
- Performance, power, energy and heat/temperature models;
- Dynamic Voltage and Frequency Scaling (DVFS)
- Power/clock gating strategies;
- Performance vs. power/energy scaling and management.

- Programing languages, compilers and models for heterogeneous and energy-aware computing;
- Profiling and simulation tools for heat/power/energy estimation;
- Scheduling, mapping and task/thread migration policies for performance and power/energy optimization;
- Performance- and energy-aware resource management;
- Operating system support and energy management tools.

Submitted papers must be formatted according to the rules of the Springer Series Lecture Notes in Computer Science (LNCS).

Please note that papers (for conference presentation) must not exceed 8 pages in length, when typeset using the LNCS format. Accepted papers will be distributed in electronic format to participants of VECPAR'2016 and PPEO'2016.

Papers presented at the workshops will be published under the Springer LNCS series. The authors may be asked to revise the paper after the conference in order to meet the series requirements.

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