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HARSH 2016 : Workshop on Highly-Reliable Power-Efficient Embedded Designs


When Mar 12, 2016 - Mar 12, 2016
Where Barcelona (Spain)
Submission Deadline Jan 22, 2016
Notification Due Feb 8, 2016
Final Version Due Feb 26, 2016

Call For Papers

HARSH 2016
Workshop on Highly-Reliable Power-Efficient Embedded Designs


March 12th 2016, Barcelona (Spain)
In conjunction with HPCA 2016, CGO 2016, and PPoPP 2016



HARSH 2016 will provide a unique forum for the discussion of the
challenges in the design and operation of harsh environment-capable
embedded processors.

Nowadays, embedded chips are deployed almost everywhere, from mobile
phones to on-board electronics in automobiles and satellites.
Different from conventional microprocessor designs, the operation
conditions of embedded processors are severely constrained by the
environment. For example, in aerospace applications, the computer
installed on Mars rover "Curiosity" has to tolerate extreme space
radiation and temperatures, operate at low power, and provide enough
computation capability to perform mission-critical tasks. Embedded
designs for Unmanned Aerial Vehicles (UAVs) also encounter extremely
challenging design requirements. Despite their tight power budget,
UAV chips demand significant throughput for real-time high-speed
image processing. In the context of oil and gas exploration and
extraction, embedded processors can be found even on the drill string
itself, to process sensor inputs in real time while withstanding high
temperatures and humidity levels.

To guarantee reliability across these drastically diverse
environments, the design and operation of embedded processors should
not be solely confined to the chip but traverse different layers in
the computing system, involving firmware, operating system,
applications, as well as power management units and communication
interfaces. The goal of HARSH 2016 is to facilitate the exchange of
the latest ideas, insights, and knowledge related to all critical
aspects of new-generation harsh environment-capable embedded
processors, including micro-architectural approaches, cross-stack
hardware/software techniques, and emerging challenges and
opportunities. We hope to attract a group of interdisciplinary
researchers from academia, industry, and government research labs.

In addition to the presentation of selected paper submissions,
keynote speakers will be invited to kick-off the workshop sessions
and a "Best Paper" award will be presented at the conclusion of the
workshop. To encourage discussion between participants, HARSH 2016
will organize dedicated programs for discussion between presenters
and the audience.


Topics of interest include but are not limited to:

(1) Architecture design and implementation for highly-reliable
power-efficient embedded processors:
- Architectural approaches for reliability assurance under
very-low power budgets.
- Availability, soft-error tolerance and recovery issues.
- Highly-reliable cache/memory hierarchies.
- Massive heterogeneous processing capabilities.
- Power management techniques.
- Very-low power, reliable real-time processing.
- Specialized accelerator architectures and unique designs.
- Reusable and/or reconfigurable embedded designs.
- Packaging and cooling.

(2) Cross-stack hardware/software techniques:
- Cross-stack approaches for reliability assurance under
very-low power budgets.
- Reliability- and power-aware operating systems, compilers,
workload managers, firmware and other software.
- Workload analysis and optimization for reliable low-power
embedded systems.

(3) Applications:
- Aerospace: unmanned aerial vehicles (UAVs), planetary rovers
and space probes, satellites, avionic systems, etc.
- Medical support: lifesaving monitors, portable medical devices,
high-end imaging systems, etc.
- Oil and gas exploration and extraction: unmanned underwater
vehicles (UUVs), measurement while drilling (MWD), logging
while drilling (LWD), etc.
- Aerial surveillance.
- Disaster search, rescue, and relief.
- Novel applications for highly-reliable low-power embedded


Papers reporting original research results pertaining to the above
and related topics are solicited. Full paper manuscripts must be in
English of up to 6 pages (using the IEEE two-column format). The
on-line submission site is EasyChair. If web submission is not
possible, please contact the program co-chairs for alternate

To submit regular papers to the workshop, please visit:

If you have questions regarding submission, please contact us:

Important Dates:

- Submission deadline: Jan 22, 2016
- Notification of acceptance: Feb 8, 2016
- Final paper submission: Feb 26, 2016
- Workshop date: Mar 12, 2016


- Augusto Vega (IBM Research)
- Xuan (Silvia) Zhang (Washington University in St. Louis)
- David Brooks (Harvard University)
- Alper Buyuktosunoglu (IBM Research)
- Pradip Bose (IBM Research)

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