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IJHPSA 2016 : Special Issue on On-Chip Communication: Theory and Applications

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Link: http://www.inderscience.com/info/ingeneral/cfplist.php?jcode=ijhpsa
 
When N/A
Where N/A
Submission Deadline Jun 1, 2016
Notification Due Sep 1, 2016
Final Version Due Dec 1, 2016
Categories    system-on-chip   network-on-chip   multi-processor system-on-chip   interconnection networks
 

Call For Papers

Call for papers

International Journal of High Performance Systems Architecture

Special Issue on: “On-Chip Communication: Theory and Applications”

Guest Editors:
Dr. Luiza de Macedo Mourelle, State University of Rio de Janeiro, Brazil
Dr. Nader Bagherzadeh, University of California, Irvine, USA

In a System-on-Chip (SoC) design and specially in a Multi-Processor System-on-Chip (MPSoC) design, one of the main issues is the interconnection among components, from point-to-point to 3D Network-on-Chip (NoC). The decision of which kind of interconnection to apply can be based on power consumption, performance, cost and design cycle time. The increasing complexity of applications directly impacts the complexity of on-chip communication, demanding modeling and simulation of new design strategies to optimize design parameters.

This special issue invites original research related to on-chip communication theory and its applications. It welcomes both theoretical and applied papers on all aspects of design.

Subject Coverage

The following topics are recommended but not limited to:

• Communication-centric Design Flow;
• Bus-based Communication Architectures;
• Current Design Approaches;
• Physical and Electrical Analysis;
• Models for Performance Exploration;
• Power/Energy Exploration;
• Design and Synthesis of Communication Architectures;
• Dynamic Bus Reconfiguration;
• Bus Encoding Techniques;
• Interface Synthesis and Optimization;
• Secure On-chip Communication Infrastructure;
• Custom Bus Design;
• Network-on-Chips;
• Optical Interconnects;
• Wireless Interconnects;
• Physical Design Trends;
• Communication Architecture for Multi-Processor System-on-Chip;
• On-Chip Communication in 3D Architectures;
• Hybrid Networks;
• Mapping and Scheduling Tasks;
• Reliability and Fault-Tolerance.

Notes for Prospective Authors

Submitted papers should not have been previously published nor be currently under consideration for publication elsewhere. All papers are refereed through a peer review process and must be submitted online. To submit a paper, please, read our Submitting articles page. If an idea that has been published in another venue is submitted for this call, it must have substantial differences with the previously published results in the range of at least 40% in terms of added new results and the content of the paper.


Important Dates

Submission of manuscripts: 1 March, 2016

Notification of acceptance: 1 June, 2016

Final version due (tentative): 1 September, 2016

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