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OCPNBS 2016 : 7th Special Session on On-Chip Parallel and Network-Based Systems within PDP 2016

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Link: http://www.pdp2016.org/SS8.html
 
When Feb 17, 2016 - Feb 19, 2016
Where Heraklion Crete, Greece
Submission Deadline Sep 1, 2015
Notification Due Oct 19, 2016
Categories    networks-on-chip   on-chip parallel programming   computer architecture   test and reliability
 

Call For Papers

General Scope
On-chip parallel and network-based system design to achieve functionality with low energy-speed product requires larger device count SoC design, multi block function design methodology, architectures and energy evaluation schemes. Such systems, which are emerging as the architecture of choice for future high performance processors, require high performance interconnects which are necessary to satisfy the data supply needs of all cores. This session is dedicated to research on on-chip communication technology, architecture, design methods and applications, bringing together scientists and engineers working on on-chip innovations from related research communities, including parallel computer architecture, networking, and embedded systems. Original papers describing new and previously unpublished results are solicited on all aspects of on-chip parallel and networked system technology. Topics of interest include, but are not limited to:

• On-chip network architecture (topology, routing, arbitration, ...)
• Network design for 3D stacked logic and memory
• Processor allocation and scheduling in CMPs
• Mapping of applications onto NoCs
• NoC reliability issues
• OS and compiler support for NoCs
• Performance and power issues in NoCs
• Metrics, benchmarks, and trace analysis for NoCs
• Multi/many-core workload characterization and evaluation
• Modeling and simulation of on-chip parallel and networked systems
• Synthesis, verification, debug and test of SoCs
• NoC support for memory and cache access
• SoC and NoC design methodologies and tools
• Network support for SoC quality of service
• On-chip systems for FPGAs and structured ASICs
• NoC support for CMP/MPSoCs
• Floorplan-aware NoC architecture optimization
• Application-specific NoC design
• Networked SoC case studies
• On-chip parallel programming models and tools
• Reconfigurable SoCs and NoCs
• Memory system design and optimizations for SoCs
• Early reports on system prototypes details
• SIMD parallel VLSI computing
• I/O interconnects and support for SoCs
and other related topic

Important dates
Paper submission: 1 September 2015
Acceptance notification: 19 October 2015
Camera ready due: 10 November 2015
Conference: 17-19 February 2016

Organizers
Nader Bagherzadeh (UC-Irvine, USA)
Hamid Sarbazi-Azad (Sharif University of Technology, Iran)
Masoumeh Ebrahimi (KTH, Sweden and University of Turku, Finland)
Masoud Daneshtalab (KTH Royal Institute of Technology, Sweden)

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