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VPA 2015 : 2nd Workshop on Visual Performance Analysis (VPA)


When Nov 20, 2015 - Nov 20, 2015
Where Austin, TX
Submission Deadline Aug 5, 2015
Notification Due Sep 8, 2015
Final Version Due Oct 5, 2015

Call For Papers

Call for Papers

2nd Workshop on Visual Performance Analysis (VPA)
Held in conjunction with SC15:
The International Conference on High Performance Computing,
Networking, Storage and Analysis

Austin, TX, USA
November 20, 2015

EXTENDED Submission Deadline: August 5, 2015

Over the last decades an incredible amount of resources has been devoted
to building ever more powerful supercomputers. However, exploiting the
full capabilities of these machines is becoming exponentially more
difficult with each new generation of hardware. To help understand and
optimize the behavior of massively parallel simulations the performance
analysis community has created a wide range of tools and APIs to collect
performance data, such as flop counts, network traffic or cache behavior
at the largest scale. However, this success has created a new challenge,
as the resulting data is far too large and too complex to be analyzed in
a straightforward manner. Therefore, new automatic analysis approaches
must be developed to allow application developers to intuitively
understand the multiple, interdependent effects that their algorithmic
choices have on the final performance.

This workshop will bring together researchers and practitioners from the
areas of performance analysis, application optimization, visualization,
and data analysis and provide a forum to discuss novel ideas on how to
improve performance understanding, analysis and optimization through
novel techniques in scientific and information visualization.

Workshop Topics:

- Scalable displays of performance data
- Interactive visualization of performance data
- Data models to enable data analysis and visualization
- Graph representation of unstructured performance data
- Collection and representation of meta data to enable fine
grained attribution
- Message trace visualization
- Memory and network traffic visualization
- Representation of hardware architectures

Paper Submission:

We solicit two types of papers both covering original and previously
unpublished ideas: 8 page regular papers and 4 page position papers.
To be considered, your manuscript should be formatted according to
the double-column IEEE format for Conference Proceedings (IEEEtran
LaTeX Class (template) V1.8 packages and IEEEtran V1.12 BibTeX
(bibliography)). Margins and font sizes should not be modified. The
templates for "IEEEtran LaTeX Class (template) V1.8 packages and
IEEEtran V1.12 BibTeX (bibliography)" can be found at

All papers must be submitted through Easychair at:

Important Dates

- Aug 5th: submission deadline for full papers
- September 8th: notification of acceptance
- October 5th: final paper and copyrights due

Workshop Organizers

- Peer-Timo Bremer, Lawrence Livermore National Laboratory
- Bernd Mohr, Jülich Supercomputing Centre
- Valerio Pascucci, University of Utah
- Martin Schulz, Lawrence Livermore National Laboratory



Program Committee

* Holger Brunst, ZIH / TU Dresden
* Remco Chang, Tufts University
* Hank Childs, University of Oregon
* Karl Fuerlinger, Ludwig Maximilians Universitaet
* Todd Gamblin, Lawrence Livermore National Laboratory
* Marc-Andre Hermanns, Jülich Supercomputing Centre
* Judit Gimenez, Barcelona Supercomputing Center / Universitat Politècnica de Catalunya
* Kevin Huck, University of Oregon
* Daniel Keim, Universitaet Konstanz
* Joshua Levine, Clemson University
* Naoya Maruyama, RIKEN AICS
* John Mellor-Crummey, Rice University
* Klaus Mueller, Stonybrook
* Matthias Mueller, RWTH Aachen University
* Paul Rosen, University of Utah
* Carlos Scheidegger, University of Arizona
* Derek Xiaoyu Wang, UNC Charlotte
* Felix Wolf, German Research School for Simulation Sciences

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