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VLSID 2016 : 29th IEEE International Conference on VLSI Design, 2016


Conference Series : International Conference on VLSI Design
When Jan 4, 2016 - Jan 8, 2016
Where Kolkata, West Bengal, India
Abstract Registration Due Jul 19, 2015
Submission Deadline Jul 26, 2015
Notification Due Sep 26, 2015
Final Version Due Oct 11, 2015
Categories    vlsi design   testing   embedded systems

Call For Papers

January 4-8, 2016, Kolkata, India

Apologies if you receive multiple copies of this email. The 29th International Conference on VLSI Design and the 15th International Conference on Embedded Systems will bring together industry and academia to present front-end technology under the theme of "Technologies for a Safe and Inclusive World (TSIW)".

The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Today semiconductor technology is poised to look beyond its traditional bastions of application with pervasive impact on transportation, energy, disaster management, environment, and healthcare.

The Technical tracks will be grouped under the theme track and the three broad categories namely, Design Methodologies and Technology, Design Tools and EDA and Embedded System Design and Tools. The conference proceedings will be published by the IEEE Computer Society Press. Selected papers from this conference will also be published as special issues of top archival journals.

Authors are invited to submit full-length (6 pages maximum) in IEEE CS proceedings format, original, unpublished papers with an abstract (200 words maximum) under the tracks listed below. To enable double blind review, the author list should be omitted from the main document. Papers violating length and blind-review criteria would be excluded from the review process. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered for publication.

Track: Design Methodology and Technology
D1: System-level Design
ESL, System-level design methodology, Multicore systems, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect tolerant architectures

D2: Advances in Digital Design
Logic and Physical synthesis; Place & Route, Clock Tree, Physical Verification, Timing and Signal integrity, Power analysis and integrity, OCV, DFM; DFY; Challenges for advanced technology nodes

D3: Analog / RF Design
Analog Mixed Signal IP; High-Speed interfaces; SDR and wireless; Low-power Analog and RF; Effective use of Spectrum; Memory Design, Standard Cell Design

D4: Power Aware Design
Low-power design, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools

D5: Devices / Circuits
New Devices and architectures; Low power devices; Modeling and Simulation; Multi-domain simulation; Numerical methods; Device/circuit level variability models; Reliability simulation

D6: Emerging Technologies
Nano-CMOS technologies; MEMS; CMOS sensors; CAD/EDA methodologies for nanotechnology; Nano-electronics and Nano-circuits, Nano-sensors, MEMS applications, Nano-assemblies and Devices, Non-classical CMOS; Post-CMOS devices; Biomedical circuits, Carbon Nano-tubes based computing

Track : Design Tools and EDA
T1: Design Verification
Functional Verification; Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate-level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies

T2: Test Reliability and Fault-Tolerance
DFT, Fault modelling/simulation; ATPG; Low Power DFT; BIST & Repair; Delay test; Fault tolerance; Online test; AMS/RF test; Board-level and system-level test; Silicon debug, post-silicon validation; Memory test; Reliability test; static and dynamic defect- and fault-recoverability, and variation-aware design

T3: Computer-Aided Design (CAD)
Hardware/software co-design, logic and behavioural synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction)

Track : Embedded System Design and Tools
E1: Embedded Systems
Hardware/Software co-design & verification; Reconfigurable computing; Embedded multi-cores SOC and systems; Embedded software including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip; Embedded applications, Platforms & Case studies

E2: FPGA Design and Reconfigurable Systems
FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping

E3: Wireless Systems
Wireless Sensor Networks, Low Power wireless Systems, Embedded Wireless, Wireless protocols, Wireless Power / Charging

Theme Track : Technologies for a Safe and Inclusive World
H1: Technologies for Healthcare Applications
H2: Technologies for Smart Management of Energy Systems
H3: Technologies for Intelligent and Secure Transportation Systems
H4: Technologies for Safety Assurance of Embedded Circuits and Systems
H5: Technologies for Secure Embedded Circuits and Systems

Proposals for Tutorials and Special Sessions/Panel Discussion on the above-listed topics (but not limited to) are invited. Please check conference website for details.

Important dates are the following:

Abstract submission : July 19, 2015 (Sunday)
Full Paper submission : July 26, 2015 (Sunday)
Acceptance Notification : Sep 26, 2015 (Saturday)
Camera-ready version : Oct 11, 2015 (Sunday)

Tutorial Proposals : July 19, 2015 (Sunday)
Acceptance Notification : Sep 26, 2015 (Saturday)
Presentation Slides : Nov 15, 2015 (Sunday)

Proposal submission : July 19, 2015 (Sunday)
General Chairs
Pradip Bose, IBM
Susmita Sur-Kolay, ISI

Vice-General Chairs
Indranil Sengupta, IITKGP
Parthasarathi Dasgupta, IIMC

Program Chairs
Krishnendu Chakrabarty, Duke
Pallab Dasgupta, IITKGP
Partha P. Das, IITKGP

Tutorial Chairs
Hafizur Rahaman, IIEST
Prabhat Mishra, UF
Annajirao Garimella, Intel

Publiciy chairs
Chandan Giri, IIESTS
Ken Stevens, U. Utah
Monica Pereira, UFRN
Robert Wille, U. Bremen
Swarup Bhunia, CWRU
T. -Y. Ho, NCKU

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