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ReConFig 2015 : Reconfigurable Computing and FPGAs


Conference Series : Reconfigurable Computing and FPGAs
When Dec 7, 2015 - Dec 9, 2015
Where Cancun, Mexico
Submission Deadline Aug 10, 2015
Notification Due Sep 18, 2015
Final Version Due Oct 16, 2015

Call For Papers


*** Final Deadline Extensions! ***
*** Abstract Submission Deadline: August 3rd ***
*** Final Paper Submission Deadline: August 10th***

¡Celebrating ReConFig's 10th Edition!

ReConFig 2015

2015 International Conference on ReConFigurable Computing and FPGA's December 7-9, 2015, Mayan Riviera, Mexico.

* 3 Keynote Speeches
* Technical Sessions (General Sessions + 8 Special Tracks)
* PhD Forum
* Demo Night
* Social Events

IEEE CASS Technical Cosponsorship.

Conference Proceedings by the IEEE, to be included in IEEE Digital library (IEEE Xplore). Special Issues of International Journals.

Deadline for Abstract Submissions: August 3rd, 2015 (Final Deadline Extension)
Deadline for Full Paper Submission: August 10th, 2015 (Final Deadline Extension)


Call for Papers

It is our pleasure to invite you to participate in the 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig
2015) that will be held December 7-9, 2015 in the Mayan Riviera, Mexico.

Reconfigurable computing and FPGA technology have become major subjects of research in computing and electrical engineering as they have been identified as powerful alternatives for creating highly efficient computing systems. Reconfigurable computing offers substantial performance improvements when compared against traditional processing architectures via custom design and reconfiguration capabilities.
Reconfiguration is characterized by the ability of hardware architectures or devices to rapidly alter the functionalities of its components and the interconnection between them as needed. Existing theoretical models and algorithms combined with commercially available devices, such as FPGAs, make Reconfigurable Computing a very powerful computing paradigm.


ReConFig is one of the leading forums in the field that brings together an appropriate mix of all theoretical and practical aspects of reconfigurable computing and FPGA technology. The conference promotes the use of reconfigurable computing and FPGAs devices for research, education, and applications, covering from hardware architectures and devices to custom computers and high performance systems.

ReConFig covers a broad spectrum of topics including, but not limited to:

* Models, methods, tools, and architectures for reconfigurable computing
* Compilation, simulation, debugging, synthesis, verification, and test of reconfigurable systems
* Field programmable gate arrays and other reconfigurable technologies
* Evolvable hardware and dynamic reconfiguration
* Algorithms implemented on reconfigurable hardware
* Reconfigurable computing education
* Reconfigurable computing applications

In addition to the general session, submissions are invited for the following tracks:

* Coarse Grained Reconfigurable Computing: Architectures and Programming Models
* Cyber Physical Systems
* High Performance Reconfigurable Computing
* Multiprocessor Systems and Networks on Chip
* Productivity Environments and High Level Languages
* Reconfigurable Computing for DSP and Communications
* Reconfigurable Computing for Security and Cryptography
* Reconfiguration techniques
* Phd Forum

Demo Night
All attendees will be encouraged to bring their hardware/software for display at the ReConFig 2015 Demo Night.

Conference Proceedings
Conference Proceedings will be edited by the IEEE and will appear at IEEE Xplore Digital Library. Authors of selected papers will be invited to submit an extended version for a ReConFig’15 Special Issue of International Journals (TBC).

Submission information
Regular submissions should be no more than 6 pages long including tables, figures and references. They have to be submitted for evaluation as a PDF file using IEEE formatting.

Important Dates

Abstract Submissions: August 3rd, 2015 (Final Deadline Extension)
Full Paper Submission: August 10th, 2015 (Final Deadline Extension)

Acceptance Notification: September 18, 2015
Final paper submission: October 16, 2015
Conference: December 7-9, 2015

Organizing Committee

General Chair
René Cumplido, INAOE, Mexico

Program co-Chairs
Maya Gokhale, Lawrence Livermore National Laboratory, USA Michael Huebner, Ruhr University Bochum, Germany

Proceedings Chair
Claudia Feregrino, INAOE, Mexico

Tracks co-Chairs
Hugo Andrade, National Instruments, USA
Peter Athanas, Virginia Tech, USA
Zain-ul-Abdin, Halmstad University, Sweden Jason Bakos, University of South Carolina, USA João Cardoso, University of Porto, Portugal Eduardo de la Torre, Technical University of Madrid, Spain Kris Gaj, George Mason University, USA Diana Göhringer, Ruhr University Bochum, Germany Tim Güneysu, Ruhr University Bochum, Germany Sonia Lopez Alarcon, Rochester Institute of Technology, USA Thilo Pionteck, University of Lübeck, Germany Mario Porrmann, Bielefeld University, Germany Marco Santambrogio, Politecnico di Milano, Italy Andrew Schmidt, ISI/USC, USA Hayden So, The University of Hong Kong, Hong Kong Mike Wirthlin, Brigham Young University, USA

Related Resources

ICSC 2018   12th IEEE International Conference on Semantic Computing (ICSC 2018)
CHI 2018   ACM CHI Conference on Human Factors in Computing Systems
IPMU 2018   17th Information Processing and Management of Uncertainty in Knowledge-Based Systems Conference
IPCCC 2017   International Performance, Computing, and Communications Conference
DRSN 2017   International Workshop on High Performance Dynamic Reconfigurable Systems and Networks
ICAISC 2018   International Conference on Artificial Intelligence and Soft Computing
ARC 2017   13th International Symposium on Applied Reconfigurable Computing
ReCoSoC 2017   12th Edition of the International Symposium on Reconfigurable Communication-centric Systems-on-Chip
ParaFPGA 2017   Parallel Computing with FPGAs
FPL 2017   Field Programmable Logic and Applications - call for workhops