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ParaFPGA 2015 : Parallel Computing with FPGAs

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Link: http://parafpga2015.elis.ugent.be
 
When Sep 1, 2015 - Sep 4, 2015
Where Edinburgh, Scotland, UK
Submission Deadline Jun 1, 2015
Notification Due Jul 15, 2015
Final Version Due Aug 15, 2015
Categories    FPGA   high performance computing   parallel processing   high level synthesis
 

Call For Papers

ParaFPGA2015 is a Mini-Symposium organized in conjunction with the biennial Parallel Computing conference ParCo2015, to be held in Edinburgh, Scotland, UK on 1-4 September 2015.

SCOPE

ParaFPGA focuses on parallel techniques for using FPGAs as accelerator in high performance computing areas such as supercomputing, embedded systems and big data computing.

Field Programmable Gate Arrays emerge as powerful building blocks for High Performance Systems. The freedom to build tailored architectures with extremely low power is one of the key milestones on the path to exascale processing. Recently the major industrial players invested heavily in high-level synthesis tools and established well known programming paradigms to facilitate the march towards programmable hardware. In addition, the famous memory wall has been alleviated by incorporating processing cores inside the FPGA fabric.

Of special interest are design methods, heterogeneous architectures and algorithms optimized for execution on FPGAs. Design methods include optimizing the resource utilization, development time and high-level synthesis tools. Heterogeneous architectures aim at multi-FPGAs, FPGAs with CPU cores and systems combining FPGAs, GPUs and CPUs. Algorithms ready-made for FPGAs range from streaming applications to fast dynamic reconfiguration and feature a substantial performance increase.

Researchers and practitioners are invited to submit novel contributions in the areas of high-level synthesis, dynamic reconfiguration and high performance applications. Papers are invited on a wide variety of topics related but not limited to:

- high-level synthesis techniques and case studies
- optimizing throughput of streaming applications
- non-uniform memory partitioning and data reuse
- dataflow engines for irregular applications
- heterogeneous on-chip processor and programmable logic codesign
- evaluating performance metrics for high-level synthesis
- scalability of multi-core with multi-FPGA architectures
- OpenCL for FPGA applications
- high-level synthesis guided design space exploration
- high-level partial and dynamic reconfiguration
- performance-driven resource and area optimization

PAPERS

Authors are invited to submit a full paper (maximum 10 pages) or an extended abstract of minimal 4 pages. The approved contributions will be presented at the conference and the accepted full papers are published in the ParCo 2015 proceedings.

Details regarding the format, presentation and paper submission are given in the author guidelines available at the ParaFPGA website.

Deadline for the submission is 1 June 2015

COMMITTEES

STEERING COMMITTEE:

Gerhard Joubert, Conference Committee Chair
Frans Peters, Finance Chair

MINI-SYMPOSIUM COMMITTEE:

Dirk Stroobandt, Ghent University, Symposium chair
Erik D'Hollander, Ghent University, Program committee chair
Abdellah Touhafi, Brussels University, Program committee co-chair

PROGRAM COMMITTEE:

Abbes Amira, University of the West of Scotland, UK
Georgi Gaydadjiev, Maxeler Technologies, USA
Mike Hutton, Altera, USA
Tsutomu Maruyama, University of Tsukuba, Japan
Dionisios Pnevmatikos, Technical University of Crete, Greece
Viktor Prasanna, University of Southern California, USA
Mazen A. R. Saghir, Texas A&M University, Qatar
Donatella Sciuto, Politechnico di Milano, Italy
Sascha Uhrig, Technical University of Dortmund, Germany
Sotirios G. Ziavras, New Jersey Institute of Technology, USA

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