The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasisis on novelty and intellectual rigor.
Topics of interest include (but are not limited to): synthesis and optimization; power and timing analysis; testing, validation and verification; architectures and compilation; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies are also encouraged.
Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants. The workshop format includes pap
er presentations, posters, invited talks, lunch and dinner gatherings, and recreational activities. Submissions are made electronically through the EDAS system. Please see the website for instructions: http://www.iwls.org