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ICCD 2015 : The 33rd IEEE International Conference on Computer Design

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Conference Series : International Conference on Computer Design
 
Link: http://www.iccd-conf.com/Home.html
 
When Oct 19, 2015 - Oct 21, 2015
Where New York City, USA
Abstract Registration Due May 18, 2015
Submission Deadline May 25, 2015
Notification Due Jul 21, 2015
Final Version Due Aug 22, 2015
Categories    computer architecture   computer design
 

Call For Papers

Both, Abstract submission and Full paper submission are extended
by 1 week. New dates are given below.

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Call for Papers
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33rd IEEE International Conference on Computer Design
ICCD 2015
New York City, USA -- October 19-21
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IMPORTANT DATES:
May 18 Abstract submission
May 25 Full paper submission
July 21 Notification of acceptance
August 22 Camera-ready final paper
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http://www.iccd-conf.com

The International Conference on Computer Design encompasses a wide range
of topics in the research, design, and implementation of computer systems
and their components. ICCD’s multi-disciplinary emphasis provides an ideal
environment for developers and researchers to discuss practical and theo-
retical work covering system and computer architecture, test, verification
and security, design and technology, and tools and methodologies.

We especially encourage submissions that look forward to future systems
and technologies. Manuscripts describing original work on any topic from
the scope of ICCD are welcome. Authors are asked to submit technical
papers in accordance to the author’s instructions in one of the following
five conference tracks:

COMPUTER SYSTEMS AND APPLICATIONS:
Advanced computer architecture for general and application-specific
enhancement; Software design for embedded, mobile, general-purpose,
cloud, and high-performance platforms; IP and platform-based designs;
HW/SW codesign; Modeling and performance analysis; Support for secu-
rity, languages and operating systems; Hardware/software techniques
for embedded systems; Application-specific and embedded software
optimization; Compiler support for multithreaded and multi-core
designs; Memory system and network system optimization; On-chip and
system-area networks; Support for communication and synchronization.

PROCESSOR ARCHITECTURE:
Microarchitecture design techniques for uni- and multi-core processors:
instruction-level parallelism, pipelining, caching, branch prediction,
multithreading; Techniques for low-power, secure, and reliable process-
sors; Embedded, network, graphic, system-on-chip, application-specific
and digital signal processor design; Hardware support for processor
virtualization; Real-life design challenges: case studies, tradeoffs,
post-mortems.

LOGIC AND CIRCUIT DESIGN:
Circuits and design techniques for digital, memory, analog and mixed-
signal systems; Circuits and design techniques for high performance and
low power; Circuits and design techniques for robustness under process
variability and radiation; Design techniques for emerging process tech-
nologies (MEMs, spintronics nano, quantum, flexible electronics); Asyn-
chronous circuits; Signal processing, graphic processor and arithmetic
circuits.

ELECTRONIC DESIGN AUTOMATION:
High-level, logic and physical synthesis; Physical planning, design
and early estimation for large circuits; Automatic analysis and optimi-
zation of timing, power and noise; Tools for multiple-clock domains,
asynchronous and mixed timing methodologies; CAD support for FPGAs,
ASSPs, structured ASICs, platform-based design and NOC; DfM and OPC
methodologies; System-level design and synthesis; Tools and design
methods for emerging technologies (MEMs, spintronics, nano, quantum).

TEST, VERIFICATION AND SECURITY:
Design error debug and diagnosis; Fault modeling; Fault simulation and
ATPG; Analog/RF Testing; Statistical Test Methods; Large volume yield
Analysis and Learning; Fault tolerance; DFT and BIST; Functional, trans-
action-level, RTL, and gate-level modeling and verification of hardware
designs; Equivalence checking, property checking, and theorem proving;
Constrained-random test generation; High-level design and SoC validation.
Hardware security primitives; Side channel analysis; Logic and micro-
architectural countermeasures; Hardware security for IoT; Interaction
between VLSI test and trust.


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ICCD 2015 Organizing Committee
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General Chairs
Naehyuck Chang, KAIST, Korea
Ramesh Karri, NYU, USA

Technical Program Chairs
Sule Ozev, ASU, USA
Sung Woo Chung, Korea Univ, Korea

Special Session and Tutorial Chair
Luca Carloni, Columbia Univ, USA
Cristian Pilato, Columbia Univ, USA

Local Arrangements Chair
Michail Maniatakos, NYU-AD, UAE

Finance Chair
Siddharth Garg, NYU, USA

Registration Chairs
Eren Kursun, USA
Mingoo Seok, Columbia Univ, USA

Publicity Chairs
Ozgur Sinanoglu, NYU Abu Dhabi, UAE
Yongpan Liu, Tsinghua Univ, China
Swarup Bhunia, Case Western Reserve Univ, USA
Lars Bauer, Karlsruhe Inst. of Technology, Germany

Web Chair
Ender Yilmaz, Freescale, USA

ICCD Steering Committee
Kee-Sup Kim, Synopsys, USA (Chair)
Peter-Michael Seidel, Univ of Hawaii, USA
Sandip Kundu, Univ of Massachusetts, USA
Georgi Gaydadjiev, Chalmers University, Sweden

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