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IWLS 2014 : International Workshop on Logic & Synthesis


When May 30, 2014 - Jun 1, 2014
Where San Francisco, CA
Abstract Registration Due Feb 28, 2014
Submission Deadline Mar 7, 2014
Notification Due Apr 4, 2014
Final Version Due Apr 25, 2014
Categories    design automation   CAD   EDA

Call For Papers

The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty
and intellectual rigor.

Topics of interest include, but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants. The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities. Submissions are made electronically through EasyChair. Please see the workshop website for instructions:

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