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DSD 2015 : 18th Euromicro Conference on Digital Systems Design


Conference Series : Digital Systems Design
When Aug 26, 2015 - Aug 28, 2015
Where Funchal, Madeira, Portugal
Submission Deadline Apr 12, 2015
Notification Due Jun 8, 2015
Final Version Due Jun 29, 2015
Categories    digital design   digital systems   computer design

Call For Papers

DSD 2015 - Call for Papers

18th Euromicro Conference on Digital System Design
Funchal, Madeira, Portugal - August 26-28, 2015


The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from specification down to micro-architectures, digital circuits and VLSI implementations. It is a forum for researchers and engineers from academia and industry working on advanced investigations, developments and applications.

The conference focuses on today's and future challenges of advanced system architectures for embedded and high-performance SH/SW systems, application analysis and parallelization, design automation for all design levels, as well as, on modern implementation technologies from full custom in nanometer technology nodes, through FPGAs, to multi-core infrastructures. It covers a multitude of highly relevant design aspects from system, hardware and embedded-software specification, modeling, analysis, synthesis and validation, through system adaptability, security, dependability and fault tolerance, to system energy consumption minimization and multi-objective optimization.

Authors are kindly invited to submit their work according (but not limited) to the seven main topics of the conference main track. In addition, eleven Special Sessions (with their own coordinators and subprogram committees) do also welcome contributions in specific themes of particular interest. All papers are reviewed following guidelines, quality requirements and thresholds that are common to all committees.


- Advanced applications of embedded and cyber-physical systems
- Appl. analysis and parallelization for embedded and high-performance design
- Specification, modeling, verification and test for systems, HW and embedded SW
- Design and synthesis of systems, hardware and embedded software
- Systems-on-a-chip and networks-on-a-chip
- Programmable/re-configurable/adaptable architectures
- Important issues introduced by emerging technologies


- Flexible Digital Radio
Dominique Noguet (CEA - Minatec, FR)
- Multicore Systems: Design and Applic.
J. Sahuquillo (UPV Valencia, ES), A. Molnos (CEA LETI, FR)
- Dependability, Testing and Fault Tolerance in Digital Systems
H. Kubatova (CTU Prague, CZ), Z. Kotasek (TU Brno, CZ)
- Emerging Technologies and Circuit Synthesis
Tiziano Villa (U Verona, IT)
- Mixed Criticality System Design, Implementation and Analysis
K. Grüttner (OFFIS, DE), E. Villar (TEISA U Cantabria, ES)
- Architectures and Hardware for Security Applications
Paris Kitsos (TEI of Western Greece, GR)
- Design of Heterogeneous Cyber-Physical Systems
R. Muradore (U Verona, IT), M. Geilen, (TUE, NL)
- Advanced Systems in Healthcare, Wellness and Personal Assistance
F. Leporati (U Pavia, IT)
- Architectures and Systems for Automotive and Intelligent Transportation
S. Niar (U Valenciennes, FR)
- System Design for the Smart Grid
R. Jacobsen (Aarhus U, DK), D. Quaglia (U Verona,IT), E. Ebeid (Aarhus U,DK)
- European Projects in Digital System Design
F. Leporati (U Pavia, IT), L. Jozwiak (TUE, NL)

Call for Papers in pdf format:

Deadline for paper submission: March 29, 2015
Notification of acceptance: May 25, 2015
Camera ready papers: June 14, 2015

DSD 2015:


Authors are encouraged to submit their manuscripts to Should an unexpected web access problem be encountered, please contact the Program Chair by email (
Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the manuscript, references included.

CPS, Conference Publishing Services, publishes the (ISI indexed) DSD Proceedings, available worldwide through the IEEE Xplore Digital Library. Extended versions of selected best papers will be published in a special issue of the ISI indexed "Microprocessors and Microsystems: Embedded Hardware Design" Elsevier journal.

Lech Jozwiak (TU Eindhoven, NL) - Chairman
Krzysztof Kuchcinski (U Lund, SE)
António Nuñez (IUMA/ULPGC, ES)
Francesco Leporati (U Pavia, IT)
Eugenio Vilar (TEISA U Cantabria, ES)
José Silva Matos (U Porto, PT)

João Canas Ferreira (U Porto, PT) - Chair
Paris Kitsos (TEI West. Greece, GR) - Co-chair

José Silva Matos (U Porto, PT) - Chair
José Carlos Alves (U Porto, PT) - Co-chair

Hélio Mendonça (U Porto, PT)

A. Skavhaug (Norwegian UST, NO)

P. Athanas (Virginia Tech, US)
H. Basson (U. Littoral, FR)
T. Basten (TU Eindhoven, NL)
N. Bergmann (U Queensland, AU)
C. Bouganis (Imp. Coll., UK)
P. Carballo (ULPGC, ES)
L. Chen (NTU, TW)
T. Chen (Colorado St., US)
G. Danese (U Pavia, IT)
L. Fanucci (U Pisa, IT)
J. Ferreira (U Porto, PT)
M. Figueroa (U Concepcion, CL)
K. Gaj (George Mason U, US)
P. Gao (Aries Design, US)
V. Goulart (U Kyushu, JP)
G. Jacquemod (U Nice-Sophia, FR)
J. Haid (Infineon, AT)
I. Hamzaoglu (U Sabanci, TR)
A. Hemani (KTH, SE)
D. Houzet (Grenoble IT, FR)
L. Jozwiak (TU Eindhoven, NL)
B. Juurlink (TU Berlin, DE)
K. Kent (U New Brunswick, CN)
P. Kitsos (TEI of Western Greece, GR)
Z. Kotasek, (TU Brno, CZ)
H. Kubatova (CTU Prague, CZ)
K. Kuchcinski (U Lund, SE)
S. Kumar (U Jonkoping, SE)
A. Kumar (NUS, SG)
A. Lastovetsky (U Coll Dublin, IE)
J. Lee (U Chosun, KR)
F. Leporati (U Pavia, IT)
S. Lopez (ULPGC, ES)
E. Martins (U Aveiro, PT)
J. Matos (U Porto, PT)
V. Muthukumar (U Nevada, US)
N. Nedjah (U Rio de Janeiro, BR)
H. Neto (UT Lisboa, PT)
S. Niar (U Valenciennes, FR)
D. Noguet (CEA, FR)
A. Nuñez (ULPGC, ES)
O. Ozturk (U Bilkent, TR)
S. Parameswaran (U South Wales, AU)
A. Pawlak (ITE&SUT, PL)
A. Postula (U Queensland, AU)
Y. Qu (Mediatek, FI)
D. Quaglia (U Verona, IT)
D. Rossi (U Bologna, IT)
J. Sahuquillo (U Pol Valencia, ES)
J. Schmidt (CTU Prague, CZ)
C. Silvano (Pol Milano, IT)
A. Skavhaug (Norwegian UST, NO)
N. Sklavos (TEI of Western Greece, GR)
L. Sousa (UT Lisboa, PT)
W. Stechele (TU Munich, DE)
A. Tokarnia (U Campinas, BR)
R. Ubar (IT Tallin, EE)
M. Valero (U Pol Catalunya, ES)
M. Velev (Aries Design, US)
H. Vierhaus (BTU Cottbus, DE)
T. Villa (U Verona, IT)
E. Villar (U Cantabria, ES)
S. Vitabile (U. Palermo, IT)
C. Wang (USTC, CN)
C. Wolinski (IRISA, FR)
A. Yurdakul (U Bogazici, TR)

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