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PLC 2015 : Programming Models, Languages and Compilers for Manycore and Heterogeneous Architectures (Co-located with IPDPS 2015)


When May 25, 2015 - May 25, 2015
Where Hyderabad, India
Submission Deadline Jan 12, 2015
Notification Due Feb 13, 2015
Final Version Due Feb 28, 2015

Call For Papers

Call for Papers

Three essential pillars to successful parallel computing - Productivity, Portability, Performance. Creating software for heterogeneous systems can be quite complex especially when the low-level details need to be managed and abstracted from the programmer. Emerging standards are providing an incremental development to target heterogeneous architectures, be it NVIDIA, ARM, Intel or AMD. We all know software is an expensive investment. Portability is necessary, ensuring long lifetime of the software and thus reducing the maintenance cost. Other challenges include locality and memory issues, load balancing, hiding latency with concurrency and so on.
This workshop aims to brainstorm ways to make programming heterogeneous systems less challenging and more interesting. We believe that this workshop will provide a forum for the presentation and discussions of research on all aspects of heterogeneous systems programming models, compiler optimizations, language extensions, and software tools for such systems.

Areas of interest include but are not limited to the following topics:

Multicore processors, Heterogeneous systems, Accelerators
Programming models: thread and task based models, data parallel models, stream programming
Programming environments for heterogeneous systems
OpenMP for Accelerator
OpenHMPP and other related models
Compiler optimizations and tuning heterogeneous systems
Parallelization and loop transformations
Locality optimizations
Reducing synchronization and scheduling overheads on heterogeneous systems
Tiling, parametric tiling and offloading
Runtime systems for multicore processors, heterogeneous systems, accelerators
Debuggers, and performance analysis tools for heterogeneous system and accelerators
Application and Benchmarks

Important Dates:

Paper Submission Deadline: January 12th, 2015
Paper Acceptance Notification: February 13th, 2015
Camera Ready Due: February 28th, 2015
Workshop Date: May 25th, 2015

Submission Guidelines

Papers should present original research and should provide sufficient background material to make them accessible to the broader community.

Submitted manuscripts may not exceed ten (10) single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references (Please check IPDPS Call for Papersfor more details). All papers will be peer-reviewed.The complete symposium and workshop proceedings will be published and available in the IEEE Digital Library.

Papers should be submitted electronically through the workshop web site at easychair:EasyChair for PLC15


General Chair:
Barbara Chapman, University of Houston, US

Steering Committee:

Guang R. Gao, University of Delaware, US
Xinmin Tian, Intel, US
Wenguang Chen, Tsinghua University, China
Michael Wong, IBM, Canada

Program Chair and Co-Chair(s):

Sunita Chandrasekaran, University of Houston, US

Program committee:

Matthias Muller, TU Dresden, Germany
John Lidel, Micron, US
James Beyer, Cray Inc, US
Yuan Lin, NVIDIA, US
Guido Juckeland, TU Dresden
Kamesh Madduri, Pennsylvania State University, US
Piotr Luszczek, University of Knoxville, Tennessee
Seeyong Lee, Oak Ridge National Laboratory, US
Henry Jin, NASA, US
Barry Rountree,LLNL
Stephen Olivier,Sandia National Laboratories, US
Dounia Khaldi,University of Houston, US
Jeff Hammond,Intel, US
Yin Lu Texas Tech University, US

Publicity Chair:
Rezaul Karim Raju, University of Houston, US

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