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HEART 2015 : International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies

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Link: http://www.isheart.org/HEART2015/
 
When Jun 1, 2015 - Jun 2, 2015
Where Boston MA, USA
Submission Deadline Mar 6, 2015
Notification Due Apr 1, 2015
Final Version Due Apr 15, 2015
Categories    power-efficient   accelerator   FPGA   gpu
 

Call For Papers

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HEART2015 (http://www.isheart.org):
International Symposium on
Highly Efficient Accelerators and Reconfigurable Technologies
1-2 June 2015 @ Boston MA, USA

HEART2015 Design Contest (http://lut.eee.u-ryukyu.ac.jp/dc15/)
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Important dates (Technical Program):
- Paper submission due: March 6, 2015 (firm deadline)
- Author notification: April 6, 2015
- Camera-ready due: April 20, 2015
- Symposium Dates: June 1-2, 2015

Important dates (Design Contest):
- Regular papers due: March 10, 2015
- Acceptance Notification (for regular paper submission): April 1, 2015
- Camera-ready/Author Registration: April 15, 2015
- Abstract submission due: April 1, 2015
- Acceptance Notification (for abstract submission): April 15, 2015


The Sixth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:

Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices
- Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation
- Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
- Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more
- Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devices

Software and applications:
- Novel applications of high-performance computing and Big-data processing with efficient acceleration and custom computing
- System software, compilers and programming languages for efficient acceleration systems / platforms, including many-core processors, GPUs, FPGAs and other reconfigurable /custom processors
- Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems

In order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.

We are planning to organize special sessions on HPC, Big data, and Dynamic Reconfiguration. When submitting a paper, please select topic(s) if the paper is related to them. Note that regardless of the selection of special session topic(s), your paper will undergo the same peer-review process as the main technical track.

As in previous HEART editions, we plan to publish selected accepted papers at HEART 2015 in post-proceedings ACM SIGARCH Computer Architecture News (CAN), which is also available in ACM Digital Library.

Prospective authors are invited to submit original and unpublished contributions as 6-page papers to be considered as regular papers or 4-page papers to be considered as poster papers. All contributions must be submitted electronically in PDF format (two columns, US letter size, single-spacing, 10 points for main body text). For double-blind review, manuscripts must NOT identify the authors in any way, so author names, affiliations, e-mail addresses and self-references should be blanked out. Papers that identify authors may be rejected without review. You can submit your contribution(s) by following this easychair submission link.

Each accepted paper MUST have at least one author with a regular registration for the manuscript to be included and published in the symposium proceedings and ACM SIGARCH CAN post-proceedings. Authors are also expected to attend and present their paper(s) at the symposium.

The HEART2015 paper template can be download from

MS-Word: http://www.isheart.org/HEART2015/heart2015.doc
Latex: http://www.isheart.org/HEART2015/heart2015.cls

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FPGA Design Contest 2015 (Blocus Duo)

Following the FPGA design competition in HEART2014, we are planning another Blokus Duo design contest. The details of HEART2015 contest regulation has been posted on HEART2015 Web site (http://lut.eee.u-ryukyu.ac.jp/dc15/). If you are interested in the previous contest, please refer to HEART 2014 Design Contest:
http://lut.eee.u-ryukyu.ac.jp/dc14/
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Organizing Committee
General Co-chairs:
Martin Herbordt, Boston University, US
Miriam Leeser, Northeastern University, US

Vice chair:
Martin Margala, UMass Lowell, US

Technical program co-chairs:
Jason Anderson, University of Toronto, CA
Suhaib Fahmy, Nanyang Technological University, SG
Wim Vanderbauwhede, University of Glasgow, UK

Publicity co-chairs:
David Thomas, Imperial College London, UK
Yoshiki Yamaguchi, University of Tsukuba, JP

Publication co-chairs:
Yuichiro Shibata, Nagasaki University, JP

Design contest co-chairs:
Yasunori Osana, University of the Ryukyus, JP
James Goebel, Boston University, US

Local arrangement:
Gabriella McNevin, Boston University, US

Technical Program Committee (TBD)
Jason Anderson, University of Toronto, CA
Suhaib Fahmy, Nanyang Technological University, SG
Wim Vanderbauwhede, University of Glasgow, UK
Sai Rahul Chalamalasetti, Hewlett Packard, US
Ray C.C. Cheung, City University of Hong Kong, HK
Florent de Dinechin, INSA Lyon, FR
Diana Goehringer, Ruhr-University Bochum, DE
Gary Grewal, University of Guelph, CA
Toshihiro Hanawa, University of Tokyo, JP
Yuko Hara-Azumi, Tokyo Institute of Technology, JP
Masanori Hashimoto, Osaka University, JP
Brad L. Hutchings, Brigham Young University, US
Tomonori Izumi, Ritsumeikan University, JP
Peter Andrew Jamieson, Miami University, US
Nachiket Kapre, Nanyang Technological University, SG
Christos Kartsaklis, Oak Ridge National Labs, US
Kenneth Kent, University of New Brunswick, CA
Joo-Young Kim, Microsoft Research, US
Dirk Koch, University of Manchester, UK
Herman Lam, University of Florida, US
Philip Leong, University of Sydney, AU
Tsutomu Maruyama, University of Tsukuba, JP
Smail Niar, University of Valenciennes, FR
Gregory D. Peterson, University of Tennessee, US
Soojung Ryu, Samsung Advanced Institute of Technology, KR
Kentaro Sano, Tohoku University, JP
Hayden Kwok-Hay So, University of Hong Kong, HK
Ioannis Sourdis, Chalmers University of Technology , SE
Henry Styles, Xilinx, US
Bharat Sukhwani, IBM Thomas J. Watson Research Center, US
Hiroyuki Takizawa, Tohoku University, JP
David Thomas, Imperial College, London, UK
Vivek Venugopal, United Technologies Research Center, US
Tao Wang, Peking University, CN
Yu Wang, Tsinghua University, CN
Minoru Watanabe, Shizuoka University, JP
Stephan Wong, Delft University of Technology, NL
Yoshiki Yamaguchi, University of Tsukuba, JP
Masato Yoshimi, University of Electro-Communications, JP

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