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RAW 2009 : Reconfigurable Architectures Workshop


Conference Series : Reconfigurable Architectures Workshop
When May 25, 2009 - May 26, 2009
Where Rome, Italy
Submission Deadline Oct 31, 2008
Notification Due Jan 15, 2009
Final Version Due Feb 15, 2009
Categories    reconfigurable computing

Call For Papers

The 16th Reconfigurable Architectures Workshop (RAW 2009) will be held in Rome, Italy in May 2009. RAW 2009 is associated with the 23rd Annual International Parallel & Distributed Processing Symposium (IPDPS 2009) and is sponsored by the IEEE Computers Society's Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

Run-Time Reconfiguration & Adaptive Computing: Architectures, Algorithms, Technologies

Run-Time and Dynamic Reconfiguration are characterized by the ability of underlying hardware architectures or devices to rapidly alter (on the fly) the functionalities of its components and the interconnection between them to suit the problem. Key to this ability is reconfiguration handling and speed. Though theoretical models and algorithms for them have established reconfiguration as a very powerful computing paradigm, practical considerations make these models difficult to realize. On the other hand, commercially available devices (such as FPGAs and new coarse-/multi-grain devices) appear to have more room for exploiting run-time reconfiguration (RTR). An appropriate mix of the theoretical foundations of dynamic reconfiguration, and practical considerations, including architectures, technologies and tools supporting RTR is essential to fully reveal and exploit the possibilities created by this powerful computing paradigm. RAW 2009 aims to provide a forum for creative and productive interaction between all these disciplines.

Topics of Interest

Authors are invited to submit manuscripts of original unpublished research in all areas of dynamic and run-time reconfiguration (foundations, algorithms, hardware architectures, devices, systems-on-chip (SoC), technologies, software tools, and applications).

Papers targeting entire applications and systems rather than isolated kernel implementations are especially encouraged. The topics of interest include, but are not limited to:

Models & Architectures

· Interconnect and Computation Models

· RTR Models and Systems

· RTR Hardware Architectures

· Simulation and Prototyping

· Bounds and Complexity Issues

· Heterogeneous Computing Platforms

· Fault Tolerant Computing

· High Performance Computing

Algorithms & Applications

· Algorithmic Techniques

· Mapping Parallel Algorithms

· Distributed Systems & Networks

· Multimedia (Audio, Image and Video) Processing

· Wireless and Mobile Systems

· Network Applications

· Automotive Applications

· Financial Applications

· Bioinformatics Applications

· Biology Inspired Applications

Design, Technologies & Tools

· Configurable Systems-on-Chip

· Energy Efficiency Issues

· Devices and Circuits

· Reconfiguration Techniques

· High Level Design Methods

· Languages and Compilers for Reconfigurable Computing Systems

· System Support

· Adaptive Runtime Support

· Organic Computing

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