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M2A 2014 : 6th IEEE M2A2 held with 16th IEEE HPCC, Paris, France, 20-22 August, 2014

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Link: http://conference.hpcc2014.studiocheik.fr/call-for-papers/hpcc2014/front_page
 
When Aug 20, 2014 - Aug 22, 2014
Where Paris
Submission Deadline Jun 9, 2014
Notification Due Jun 23, 2014
Final Version Due Jul 15, 2014
Categories    computer architecture   parallel computing   multicore   HPC
 

Call For Papers

=============================================================================================================
Call for Papers

The 6th IEEE International Workshop on Multicore and Multithreaded Architectures and Algorithms (M2A2 2014)
Paris, France, August 20-22, 2014
http://conference.hpcc2014.studiocheik.fr/committees/hpcc2014/front_page

In conjunction with

16th IEEE International Conference on High Performance Computing and Communications (HPCC 2014)
http://conference.hpcc2014.studiocheik.fr/
===============================================================================================================

Scope:

Multicore systems are dominating the processor market ranging from embedded to high-performance systems. Currently some processors integrate more than ten cores and, as the node shrinks in future technology generations, it is expected that the number of cores will continue increasing in future manufactured systems.
To take advantage of the high number of cores efficient load balancing and scheduling policies or strategies are required. In addition, it remains a challenge to identify and productively program applications for these systems with a resulting substantial performance improvement.
On the other hand, the system designer must trade off performance versus power consumption, which is a major concern in current microprocessors. Therefore, current design must focus on new architectures or architectural mechanisms addressing this tradeoff.
Finally, most real-time embedded applications are requiring high-performance computing and multicore and multithreaded processors are becoming the typical design choice.
The aim of this workshop is to provide a forum for engineers and scientists to address the resulting challenge and to present new ideas, applications, and experience on all aspects of multicore and multithreaded systems.
Authors are invited to submit high quality papers representing their original work in (but not limited to) the following topics targeting multicore multithreaded processors:
* Multicore and multithreaded architectures
* Power-aware multicore architectures and computing
* Embedded multicore real-time systems
* Scheduling and load balancing
* Multicore programming
* Parallel and distributed algorithms


Paper Submission and Publication
Submit original unpublished papers in PDF format at the submission system: https://www.easychair.org/conferences/?conf=m2a22014. All submitted manuscripts will be reviewed at least by three expert reviewers. Submissions will be judged on originality, technical strength, quality of presentation, and relevance to the workshop scope.
All accepted papers will be included in the HPCC-2014 workshop proceeding published by IEEE Computer Society (indexed by EI). The length of the camera-ready manuscripts will be limited to 8 pages in IEEE CS proceedings paper format. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers will not be published.
Distinguished papers accepted and presented in M2A2 2014, after further revisions, could be considered for publication in special issues of SCI indexed international journals.


Important Dates
June 09, 2014: Paper Submission Due
June 23, 2014: Notification of Acceptance/Rejection
July 15, 2014: Camera-Ready Due
August 20-22, 2014: Workshop Takes Place


General Co-Chairs
Houcine Hassan, Universitat Politecnica de Valencia, Spain
Julio Sahuquillo, Universitat Politecnica de Valencia, Spain


Steering Committee
Laurence T. Yang, St. Francis Xavier University, Canada
Jong Hyuk Park, Seoul National University of Science and Technology, Korea


Program Committee (TBC)
Hideharu Amano, Keio University, Japan
Hamid R. Arabnia, University of Georgia, USA
Saddek Bensalem, Verimag Laboratory, France
Rabie BenAtitallah, University of Valenciennes, France
Luis Gomes, Universidade Nova de Lisboa, Portugal
Roberto Giorgi, Università di Siena, Italy
Zonghua Gu, Zhejiang University, China
Rajiv Gupta, University of California Riverside, USA
Eugene John, University of Texas at San Antonio, USA
Sebastian Lopez, U. of Las Palmas G.C, Spain
Smail Niar, University of Valenciennes, France
Sabri Pllana, Linnaeus University, Sweden
Sander Stuijk, Eindhoven University of Technology, Netherlands
Zili Shao, Hong Kong Polytechnic University, Hong Kong
Kostas Siozios, National Technical University of Athens, Grece
Kenjiro Taura, University of Tokyo, Japan
Salvatore Vitabile, University of Palermo, Italy
Sami Yehia, THALES Research & Technology, France
Yang Xiang, Deakin University, Australia

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