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DPNoC 2014 : 2014 International Workshop on the Design and Performance of Networks on Chip


When Aug 17, 2014 - Aug 20, 2014
Where Niagara Falls, Ontario, Canada
Submission Deadline Mar 30, 2014
Categories    VLSI

Call For Papers

The advance in VLSI technology has led to the emergence of Systems on Chips (SoC), where a large number of intellectual property cores are integrated onto a single chip. Systems on chip are of high computing performance and how components communicate is the key issue in these systems. The bus-based approach used in traditional systems represents a bandwidth bottleneck in SoC in addition to the non-scalability problem. Therefore light weight networks, known as Network on Chip (NoC), have emerged. NoCs as a promising alternative to the bus-based approach. They have their roots form data communication networks and inherit all issues faced in data communication networks with an extra challenge which is space limitation. As a result, new challenges and issues on the design and implementation of these networks have attracted the attention of several researchers.

The workshop on the Design and Performance of Networks on Chip (DPNoC'2014) will represent an international forum for researchers from both academia and industry to expose the latest trends, research findings, and emerging issues in networks on chip.

The Workshop topics include (but are not limited to) the following:

Technology constraints on NoCs
System and Micro Architecture for NoCs
Technology constraints on NoCs
System and Micro Architecture for NoCs
Flow control
Switching techniques
Routing protocols
Network modeling and performance evaluation
Schedling and Application mapping onto NoC
NOC scalability
Fault tolerance/reliability in NoC
Wireless NoC
NoCs Applications and Design
Multi-Core Systems
Floorplanning, Scheduling, and IP Mapping
FPGA-based implementation of reconfigurable NoCs
Wireless Network-on-Chip

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