The "power wall" has forced chip and system architects to design
with smaller margins between nominal and worst-case operating
points. Dynamic power and thermal management control loops have
already become an integral part of chip and system design. New
research papers in wearout and general reliability management have
recently been published. These new generation management protocols
have, however, opened up other sources of concern: e.g. control loop
stability and robustness of the management protocols. The potential
security holes exposed by the integrated control loops and system
safety issues triggered by potential violations of power or thermal
limits are other areas of concern. We seek to motivate the research
community into adopting a holistic approach to mitigating the power
wall and the concomitant reliability-security wall.

We have coined the term "Energy-Secure System Architectures" to
cover the range of research being pursued within industry and
academia in order to ensure robust and secure functionality, while
meeting the energy-related constraints of the emerging "green
computing" era. This segmented tutorial/workshop offering, composed
of lectures provided by experts in the areas of power/thermal
management, reliability and security, provides a comprehensive view
of the hardware and software aspects of Energy-Secure System
Architectures.
This is the third year of the offering of this workshop.


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TOPICS
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This full-day tutorial/workshop is organized across the following
sub-topics:

-- Power and thermal management solutions for modern
multi-core platforms.
-- Robustness of system power/thermal managers:
verification and design for verification.
-- Reliability and security holes exposed by
power/thermal management protocols.
-- Guarded, two-level management protocols for
safety and low verification complexity.
-- Architectural implications of and system software
support for energy-secure systems.
-- Security and reliability issues in emerging low
power memory technology.


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CALL FOR LECTURES
===========================

A few eminent researchers have already offered to give invited
lectures at this year’s ESSA workshop/tutorial offering. We invite
potential other participants to send in a lecture proposal (30 mins
minimum to 75 mins maximum). The submission should include a title
and abstract, along with a bio-sketch of the speaker and the
proposed talk duration. The deadline for submission is: May 10 2013.
Please send it to the co-organizers: Alper Buyuktosunoglu, Pradip
Bose and Augusto Vega at: alperb@us.ibm.com, pbose@us.ibm.com and
ajvega@us.ibm.com. Notification of acceptance: May 17, 2013.

Speakers will be invited to prepare written articles for publication
(after review) in a post-workshop (proposed) special issue of IEEE
Micro.