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PATMOS 2013 : 23rd International Conference on Power and Timing Optimization and Simulation


Conference Series : Power and Timing Modeling, Optimization and Simulation
When Sep 9, 2013 - Sep 11, 2013
Where Karlsruhe, Germany
Submission Deadline May 31, 2013
Notification Due Jun 30, 2013
Final Version Due Jul 28, 2013
Categories    VLSI   low power   computer science   microelectronics

Call For Papers

23rd International Conference on Power and Timing Optimization and Simulation
Karlsruhe, Germany,
September 9 - 11, 2013

Call for Paper

co-located with VARI 2013, the 4th European Workshop on CMOS Variability.


PATMOS is the premier event covering all aspects of power-efficient circuits, microchips, computers and ICT infrastructures. PATMOS allows attendees to benefit from a wide range of topics covering research & development power-efficient methods of designing and running computing and sommunication architectures, subsystems, systems and infrastructures, also including heterogeneous systems.

Meanwhile, power-efficiency has become extremely important for many more areas far beyond the microchip and processor design. Energy-efficient ICT (Information and Communication Technology) infrastructures have become a critical economic factor. Already now, not only for data centers and extreme-scale supercomputers electricity consumption is often the largest cost factor. It has been predicted that during next decade, the electricity cost of running ourICT infrastructures will become unaffordable through growing by substantially more than an order of magnitude, if current trends continue.

The progress of traditional power efficiency R&D is by far too slow to break these current trends. We must discuss, how to extend our R&D landscape to detect and remove performance-efficiency barriers also by across layer approaches at and between abstraction layers and paradigm domains.

Topics of Interest

Authors are invited to submit manuscripts of original unpublished research. This year a focus is on power-efficiency. The topics of interest include, but are not limited to:

Reliability and Technology Variations
• Modeling and simulation in the presence of variability
• Variation-aware circuit design
• Reliability issues in nanoscale circuits
• Soft errors and radiation hardening
• Methods and Architectures for fault dependability
• Resilient hardware/software architectures
• Design for self adaptive circuits and systems
• Sensors for power, variability, temperature, and aging

Low Power and Thermal-aware Design
• Design techniques for thermal-aware and low power circuits and systems
• Power/thermal-aware synthesis and floorplanning
• Policies for power and thermal optimization
• Power/Thermal Estimation and Optimization
• Power/Thermal-aware architectures
• Hardware-software interaction for power/temperature minimization
• Energy-harvesting
• Low Power Systems: wireless sensor networks, mobile computing

Compilers, operating systems and runtime systems
• Power efficiency through parallelizing compilers or parallel programming
• Concepts for programming novel multi-core architectures
• Real-time system compilers, operating systems and run-time systems

FPGAs and GPU-based accelerators
• Novel accelerator-based architectures and architectural features
• High-Level Abstractions and CAD tools for using accelerators
• Neuro-Inspired Accelerators for Computing
• Customized processor instruction sets
• Compilers optimizing for dynamically reconfigurable processor arrays (DRPAs)
• Case studies and challenges on DRPAs and accelerators

Power-efficient High-performance ICT and Data Centers
• Supercomputing: compilers, operating systems, run time systems
• Hardware-software interaction for low power high-performance
• Modeling and analysis of energy costs for ICT subsystems and infrastructures
• Power analysis for data centers, supercomputers, communication networks
• Cross layer approaches and new paradigms for power efficiency in ICT
• Power-efficient I/O interfaces and NoC design
• Low power high performance in extreme scale supercomputing
• Heterogeneous HPC by new storage technologies
• Case studies: test cases, or design study challenges on data stations or supercomputers

Application-specific power efficiency by algorithmic and analytic efforts
• Banking, financial modeling and financial database acceleration
• Social networks, games, entertainment, ambient intelligence, ubiquitous and wearable computing
• Bioinformatics, bio-inspired, medical, and genetics systems and life sciences
• Physics and astronomy, weather prediction, oil and gas exploration, and more
• Security systems, cryptography, object recognition and tracking, global navigation satellite systems
• Audio/video, imaging, smart cameras, PDAs, smart image sensors, Reconfigurable Video Coding (RVC), etc.

Aerospace, avionics, automotive and railway, and many other application areas
Case studies
• ICT, wireless sensor networks, wireless health, green computing, ultra low-power embedded systems, displays
• Examples, studies or challenges presenting innovative solutions for thermal and power efficiency
• Studies and experiences in using Azido
• Studies about power efficiency in extreme scale supercomputing projects
• Studies on energy efficiency by paradigm shift, by heterogeneous solutions or new storage technologies

• Case Studies on power efficiency of data stations

New directions in CS Education
• Roadmap of reconfigurable computing: compiled accelerators, ASICs and ASIPs
• New concepts in teaching, in tutorials, novel curricula and laboratories
• Industry and academic collaborative programs
• Design techniques for thermal and low power circuits and systems at all levels of abstraction

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