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SAE World Congress/AE 2013 : SAE World Congress - Session AE318/System Level Architecture Design Tools and Methods


When Apr 16, 2013 - Apr 18, 2013
Where Detroit
Submission Deadline Sep 1, 2012
Notification Due Sep 10, 2012
Final Version Due Jan 25, 2013
Categories    electronics   software   systems   design

Call For Papers

Call for Abstracts - Session AE318/System Level Architecture Design Tools and Methods
April 16-18, 2013 - Cobo Center, Detroit, Michigan
Dear Colleagues,
You are invited to submit:
• An abstract of 500 words max that states the objective of the paper/presentation; outlines the problem requiring solution, or the method of approach to research; is explicit with respect to the types of data to be included; and summarizes the conclusions that will be made.
• A tentative title of the paper.
• The name of the author and co-authors including all contact information.

Abstracts must be submitted on-line to SAE and targeted to ONE session.
Upon submission, you will receive an automatic reply with your paper offer number.

Offered papers shall not have been published outside of SAE; and if accepted, contributors agree to not release their paper for publication through other media.

Paper acceptance will be based on organizer moderated peer review of a review ready manuscript in line with the following dates:

Deadline for submitting paper abstracts September 1, 2012
Review Ready Manuscripts due to session organizers October 23, 2012
Final Manuscripts due to SAE January 25, 2013

Session AE318 Description
This session focuses on methods and design tools for the exploration, analysis, simulation, selection, synthesis, and optimization of E/E automotive architectures (e.g., software, hardware, communication, wiring harness, and power architectures). These methods and tools apply to technologies such as multi-core processors, distributed systems, AUTOSAR, Flexray, CAN, Ethernet, and DSRC among others.
The methods and tools are usually (but not limited to) model-based and aware of underlying modeled HW/SW platform. They are usually (but not limited to) simulation, analysis, optimization, and design flow management. They are both applied in the early phases of the E/E architecture development process to compute metrics of interest e.g., timing latencies and jitter, cost, system reliability, that enable the quantitative exploration, selection, and optimization of E/E architectures and also in the later stages of the E/E architecture development process to enable model-based software and system level fast regression and integration testing as well as verification and validation of E/E architectures.
Paolo Giusto, Amit Choudhury
Session AE318 Organizers

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