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DRNoC 2012 : International Workshop on Dynamic Reconfigurable Network-on-Chip


When Jul 2, 2012 - Jul 6, 2012
Where Madrid, Spain
Abstract Registration Due Feb 22, 2012
Submission Deadline Feb 28, 2012
Notification Due Mar 21, 2012
Final Version Due Apr 11, 2012
Categories    algorithms   ener4gy   analysis

Call For Papers

-as part of the International Conference on High Performance Computing & Simulation

Emerging SoCs (System-on-Chip), such as those for mobile systems, are typically battery-powered systems and have to support a wide range of streaming applications such as video and audio. Network-on-chip (NoC) has been recently proposed for SoC applications design to achieve better performance and lower energy consumption when compared to conventional on-chip bus architectures.

Several approaches have been proposed to deal with NoC and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored an application domain or a specific application by providing an application- specific NoC. All parameters, such as the on-chip interconnect architecture
(i.e., topology), routing, and switching schemes, are defined at design time. However, NoC should be scalable and adaptive to support various applications by selecting the most suitable parameters based on the requirements of the current application and system conditions.

Recently, there has been a great deal of interest in the development of run-time approaches for reconfigurable NoC. These approaches provide techniques that allow NoC to autonomously adapt its structure and their behavior during the course of their operation (i.e., in runtime). For example, the number of VCs (virtual channels) and the buffer size per VC can be dynamically adjusted based on the traffic load and network status.

DRNoCÂ’12 workshop is intended to serve as a forum and bring together the researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of dynamic reconfigurable NoC. It will cover current and new approaches and relevant activities in the design, analysis, and evaluation of techniques for dynamic reconfigurable NoC.

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