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CASS 2012 : 2nd Workshop on Communication Architecture for Scalable Systems


When May 21, 2012 - May 21, 2012
Where Shanghai, China
Submission Deadline Dec 19, 2011
Notification Due Jan 31, 2012
Final Version Due Feb 14, 2012
Categories    computer architecture   distributed computing   interconnection networks   communication systems

Call For Papers

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The 2nd Workshop on Communication Architecture for Scalable Systems
Shanghai, China, 21 May 2012

To be held in conjunction with the International Parallel and
Distributed Symposium (IPDPS 2012)


High-speed communication is critical to all parts of an HPC system.
On-chip networks for emerging many-core processors; point-to-point
interconnects, which have replaced the system bus for intra-node
communication; and system-wide networks, which form the backbone of
any large-scale parallel system, all contribute to the construction of
the world’s fastest computers. Numerous research groups in academia,
industry, and government are currently investigating the issues
involved in improving the speed, reliability, power consumption, and
other characteristics of communication subsystems and seeking new ways
to advance the state of the art in cluster communication.

The goal of this workshop is to bring together researchers working on
improving communication at every level of the network hierarchy
(on-chip, intra-node, and cross-cluster), thereby enabling the sharing
and adaptation of ideas from what have traditionally been separate

All researchers and practitioners working in the area of communication
architectures for scalable systems are encouraged to submit a paper to
the workshop.


Topics of interest for the workshop include but are not limited to the

* Hardware and software issues related to router/switch
organization, flow control, collective communication, congestion
control, routing and deadlock handling, network topology, load
balancing, reliability, QoS support, topology discovery, dynamic
reconfiguration, energy efficiency, and clustered storage and
fileserver. Research at any level of the network hierarchy
(on-chip, intra-node, and cross-cluster) is welcome.

* Architectural and run-time system support for messaging, PGAS,
shared memory, and other programming models.

* Design and implementation of standard or custom software
communication layers for any or all parts of the network

Papers covering more than one of on-chip, intra-node, and cluster-wide
communication networks are especially sought. Results of both
theoretical and practical significance will be considered. Note,
however, that papers on topics that are too far removed from scalable
communication in HPC systems (e.g., mobile networks, intrusion
detection, peer-to-peer networks, grid/cloud computing) will be
rejected without review.


The proceedings of this workshop will be published together with the
proceedings of other IPDPS 2012 workshops by the IEEE Computer Society


Submitted manuscripts may not exceed eight single-spaced pages using a
11-point font on 8.5x11-inch pages, everything included (figures,
tables, references, etc.) and must be submitted electronically and in
either PostScript or PDF format. Submissions will be judged on
correctness, originality, technical strength, significance, quality of
presentation, and interest and relevance to the workshop attendees.
Submissions may not have appeared in or be under consideration for
another workshop, conference, or journal.

CASS manuscript submissions are being handled by EDAS. To submit a
paper, go to and follow the instructions.


Paper submission: 19 December 2011
Notification of acceptance: 31 January 2012
Camera-ready papers due: 14 February 2012
Workshop date: 21 May 2012

All deadlines are set at 11:59 p.m. anywhere on Earth
(cf., except the camera-ready due
date, which IPDPS sets as midnight PST (GMT–08:00).



* José Flich (Universidad Politécnica de Valencia, Spain)
* Scott Pakin (Los Alamos National Lab, USA)
* Craig Stunkel (IBM Research, USA)

Program Committee:

* Dennis Abts (Google, USA)
* Ahmad Afsahi (Queen’s University, Canada)
* Pavan Balaji (Argonne National Lab, USA)
* Davide Bertozzi (University of Ferrara, Italy)
* Taisuke Boku (University of Tsukuba, Japan)
* Darius Buntinas (Argonne National Laboratory, USA)
* Natalie Enright (University of Toronto, Ca-nada)
* Holger Fröning (Heidelberg University, Germany)
* Ada Gavrilovska (Georgia Tech, USA)
* Torsten Hoefler (National Center for Supercomputing Applications, USA)
* John Kim (KAIST, Korea)
* Gaspar Mora (Intel, USA)
* Raymond Namyst (University of Bordeaux & INRIA, France)
* José Luis Sánchez (University of Castilla-La Mancha, Spain)
* Federico Silla (Universidad Politécnica de Valencia, Spain)
* Tor Skeie (Simula Research Lab, Norway)
* Gabriel Tanase (IBM Research, USA)
* Jesper Larsson Träff (University of Vienna, Austria)
* Keith Underwood (Intel, USA)
* Abhinav Vishnu (Pacific Northwest National Laboratory, USA)
* Xin Yuan (Florida State University, USA)
* Eitan Zahavi (Mellanox Technologies, Israel)

Steering Committee:

* D. K. Panda (Ohio State University, USA)
* José Duato (Universidad Politécnica de Valencia, Spain)


For more information on CASS 2012 or if you have any questions please
contact the workshop organizers at

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