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VAMM 2012 : Variability modelling and mitigation techniques in current and future technologies


When Mar 16, 2012 - Mar 16, 2012
Where Dresden
Submission Deadline Nov 20, 2011
Notification Due Dec 15, 2011
Categories    integrated circuits   VLSI   nanoelectronics

Call For Papers


Friday Workshop on
Variability modelling and mitigation techniques in
current and future technologies (VAMM 2012)

Held in conjunction with
the International Conference on Design, Automation & Test in Europe
in Dresden, Germany, March 16, 2012

The influence of process variations is becoming extremely critical for nanoCMOS
technology nodes, due to geometric tolerances and manufacturing non-idealities
(such as edge or surface roughness, or the fluctuation of the number of doping
atoms). As a result, production yields and figures of merit of a circuit such
as performance, power, and reliability have become extremely sensitive to
uncontrollable statistical process variations.
Although some kind of variability has always existed and been taken into
account for designing integrated circuits, the largest impact of variability
and the greater influence of random or spatial aspects are setting up a
completely new challenge. On top of those difficulties, the deficiency of
design techniques and EDA methodologies for tackling PVs makes that challenge
even more critical. Variability has a huge economic impact in terms of yield
loss or overdesign that is increasing with each technology generation. Without
design countermeasures to reduce the impact of process variations, the cost
advantage of technology scaling will be overrun by losses due to an increasing
gap between designed and actual performances and therefore technology scaling
will not be sustainable.

A one-day Friday Workshop in conjunction with DATE 2012 will be celebrated
addressing these topics. The workshop will focus on design techniques to
counteract the problem of variability. Techniques may range from the device
level, to layout design, to architecture design. They include the use of
redundancy, regularity and reconfiguration at different description levels.

VAMM is connected with the following projects:
- ENIAC MODERN (2008-2012) -
- FP7 SYNAPTIC (2009-2012) -
- FP7 TRAMS (2010-2013) -

Research works on the topic of the workshop will be selected for interactive
presentations, in which the speaker briefly (in 10min) outlines the main
points of the work and after the session a poster is shown for discussion
and further explanations.
Topics of interest include, but are not limited to:
- Variability modelling at the device level
- Variability-aware architectures
- Redundancy techniques applied to variability and reliability
- Layout design techniques addressing variability
- Circuit synthesis for regularity
- Logic synthesis

Prospective authors are invited to submit a 2-page abstract, including figures.
Electronic submission in PDF format should be done through the workshop

Accepted papers will be chosen for a brief oral presentation (10 min),
followed by a poster session. Informal proceedings (in electronic format) will
be distributed among the participants.
Note that the Friday Workshop papers are NOT disseminated neither through the
official DATE proceedings nor through any other formal channels, such as, for
example, the IEEExplore or the ACM Digital Library.

Important dates:
- Paper submission deadline: November 20, 2011
- Notification of acceptance: December 15, 2011
- Workshop: March 16, 2012


- Antonio Rubio, Univ. Politecnica de Catalunya, Spain
- Martin Elhoj, Nangate, Denmark
- Jan van Gerwen, NXP Semiconductors, The Netherlands

Technical committee:
- Asen Asenov, University of Glasgow, United Kingdom
- Ramon Canal, Univ. Politecnica de Catalunya, Spain
- Giuseppe Desoli, STMicroelectronics, Italy
- Petr Dobrovolny, IMEC, Belgium
- Martin Elhoj, Nangate, Denmark
- Fabrizio Ferrandi, Politecnico di Milano, Italy
- Jan van Gerwen, NXP Semiconductors, The Netherlands
- Arnaud Grasset, THALES, France
- Enrico Macii, Politecnico di Torino, Italy
- Miguel Miranda Corbalan, IMEC, Belgium
- Francesc Moll Echeto, Univ. Politecnica de Catalunya, Spain
- Davide Pandini, STMicroelectronics, Italy
- Paolo Pavan, Univ. degli Studi di Modena e Reggio Emilia, Italy
- Christian Pilato, Politecnico di Milano, Italy
- Andre I. Reis, UFRGS, Brazil
- Renato P. Ribas, UFRGS, Brazil
- Antonio Rubio, Univ. Politecnica de Catalunya, Spain
- Enrico Sangiorgi, Univ. di Bologna, Italy
- Loris Vendrame, Micron Technology, Italy
- Xavier Vera, Intel, Spain
- Nigel Woolaway, Leading Edge, Italy
- Paul Zuber, IMEC, Belgium

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